Age | Commit message (Collapse) | Author |
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driver doesn't have to know that the internal block size is actually 1600
bits. This involves having the "init" state zero-extend the block data,
and having "next" only absorb the block bits for that mode.
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at odds with everything else in our system (including the register
interface to sha3_wrapper). Rather than trying to rewrite sha3, I'll
isolate it in its own little-endian universe by byte-swapping all reads
and writes.
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- modified control logic (init & next flags instead of upper address bit)
- registered output data bus
- removed 8/16/32-bit data bus switch (we can only do 32 bits, moreover
Xilinx synthesizer was too stupid to understand it)
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