| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-06-02 | Change reads from clocked to unclocked to match read timing of other cores. | Paul Selkirk | |
| 2021-06-02 | Reformatted | Paul Selkirk | |
| 2017-12-05 | Added core wrapper. | Pavel V. Shatov (Meister) | |
| 2017-12-05 | Ported core to CrypTech platform | Pavel V. Shatov (Meister) | |
| - modified control logic (init & next flags instead of upper address bit) - registered output data bus - removed 8/16/32-bit data bus switch (we can only do 32 bits, moreover Xilinx synthesizer was too stupid to understand it) | |||
| 2015-03-09 | Adding initial version of sha3 core by Bernd Paysan. | Joachim StroĢmbergson | |
 |
index : core/hash/sha3 | |
| Verilog implementation sponge construction defined in the SHA-3 hash standard | git repositories |
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