From d2d5cb5efef2b77b728b97280209121020189010 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Fri, 27 Apr 2018 15:37:14 +0200
Subject: Removed FSM and cleaned up code in W mem. Cleaned up testbenches to
 silence warnings.

---
 src/tb/tb_sha256.v | 52 +++++++++++++++++++++++-----------------------------
 1 file changed, 23 insertions(+), 29 deletions(-)

(limited to 'src/tb/tb_sha256.v')

diff --git a/src/tb/tb_sha256.v b/src/tb/tb_sha256.v
index 6377688..01aa66e 100644
--- a/src/tb/tb_sha256.v
+++ b/src/tb/tb_sha256.v
@@ -37,12 +37,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
-
 //------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
@@ -167,7 +161,7 @@ module tb_sha256();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("State of DUT");
       $display("------------");
@@ -211,7 +205,7 @@ module tb_sha256();
   //
   // Dump the state of the H registers when needed.
   //----------------------------------------------------------------
-  task dump_H_state();
+  task dump_H_state;
     begin
       $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
                dut.core.H0_reg, dut.core.H1_reg, dut.core.H2_reg, dut.core.H3_reg);
@@ -227,7 +221,7 @@ module tb_sha256();
   //
   // Toggles reset to force the DUT into a well defined state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -243,7 +237,7 @@ module tb_sha256();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr = 32'h00000000;
       error_ctr = 32'h00000000;
@@ -264,7 +258,7 @@ module tb_sha256();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_result();
+  task display_test_result;
     begin
       if (error_ctr == 0)
         begin
@@ -289,7 +283,7 @@ module tb_sha256();
   // when the dut is actively processing and will in fact at some
   // point set the flag.
   //----------------------------------------------------------------
-  task wait_ready();
+  task wait_ready;
     begin
       read_data = 0;
 
@@ -383,7 +377,7 @@ module tb_sha256();
   //
   // Read the name and version from the DUT.
   //----------------------------------------------------------------
-  task check_name_version();
+  task check_name_version;
     reg [31 : 0] name0;
     reg [31 : 0] name1;
     reg [31 : 0] version;
@@ -411,7 +405,7 @@ module tb_sha256();
   // Read the digest in the dut. The resulting digest will be
   // available in the global variable digest_data.
   //----------------------------------------------------------------
-  task read_digest();
+  task read_digest;
     begin
       read_word(ADDR_DIGEST0);
       digest_data[255 : 224] = read_data;
@@ -453,8 +447,8 @@ module tb_sha256();
         write_word(ADDR_CTRL, CTRL_INIT_VALUE);
 
       #(CLK_PERIOD);
-      wait_ready();
-      read_digest();
+      wait_ready;
+      read_digest;
 
       // We need to ignore the LSW in SHA224 mode.
       if (mode == SHA224_MODE)
@@ -502,8 +496,8 @@ module tb_sha256();
         write_word(ADDR_CTRL, CTRL_INIT_VALUE);
 
       #(CLK_PERIOD);
-      wait_ready();
-      read_digest();
+      wait_ready;
+      read_digest;
 
       // We need to ignore the LSW in SHA224 mode.
       if (mode == SHA224_MODE)
@@ -530,8 +524,8 @@ module tb_sha256();
         write_word(ADDR_CTRL, CTRL_NEXT_VALUE);
 
       #(CLK_PERIOD);
-      wait_ready();
-      read_digest();
+      wait_ready;
+      read_digest;
 
       // We need to ignore the LSW in SHA224 mode.
       if (mode == SHA224_MODE)
@@ -587,8 +581,8 @@ module tb_sha256();
       write_block(block);
       write_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
       #(CLK_PERIOD);
-      wait_ready();
-      read_digest();
+      wait_ready;
+      read_digest;
 
       if (digest_data == expected)
         begin
@@ -685,15 +679,15 @@ module tb_sha256();
     begin : sha256_top_test
       $display("   -- Testbench for sha256 started --");
 
-      init_sim();
-      reset_dut();
+      init_sim;
+      reset_dut;
 
-      check_name_version();
-      sha224_tests();
-      sha256_tests();
-      restore_state_test();
+      check_name_version;
+      sha224_tests;
+      sha256_tests;
+      restore_state_test;
 
-      display_test_result();
+      display_test_result;
 
       $display("   -- Testbench for sha256 done. --");
       $finish;
-- 
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