From bb03cc0bdc9f05bdc6c861ed5d725c6a0970ae5d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Tue, 28 Aug 2018 13:06:27 +0200
Subject: Connected the pipeline regs for t1 and t2 in the stat update logic.
 Verified functionality. Updated README after test implementation. The design
 now meets 100 MHz clock in Artix7 with speed grade -1.

---
 src/rtl/sha256_core.v | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

(limited to 'src/rtl')

diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v
index 95ad28b..048df2b 100644
--- a/src/rtl/sha256_core.v
+++ b/src/rtl/sha256_core.v
@@ -135,7 +135,10 @@ module sha256_core(
   reg          H_we;
 
   reg [31 : 0] t1_reg;
+  reg [31 : 0] t1_new;
+
   reg [31 : 0] t2_reg;
+  reg [31 : 0] t2_new;
 
   reg [5 : 0] t_ctr_reg;
   reg [5 : 0] t_ctr_new;
@@ -165,9 +168,6 @@ module sha256_core(
 
   reg ready_flag;
 
-  reg [31 : 0] t1;
-  reg [31 : 0] t2;
-
   wire [31 : 0] k_data;
 
   reg           w_init;
@@ -241,8 +241,8 @@ module sha256_core(
         end
       else
         begin
-          t1_reg <= t1;
-          t2_reg <= t2;
+          t1_reg <= t1_new;
+          t2_reg <= t2_new;
 
           if (a_h_we)
             begin
@@ -385,7 +385,7 @@ module sha256_core(
 
       ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
 
-      t1 = h_reg + sum1 + ch + w_data + k_data;
+      t1_new = h_reg + sum1 + ch + w_data + k_data;
     end // t1_logic
 
 
@@ -405,7 +405,7 @@ module sha256_core(
 
       maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
 
-      t2 = sum0 + maj;
+      t2_new = sum0 + maj;
     end // t2_logic
 
 
@@ -425,11 +425,9 @@ module sha256_core(
       f_new  = 32'h0;
       g_new  = 32'h0;
       h_new  = 32'h0;
-      a_h_we = 1'h0;
 
       if (state_init)
         begin
-          a_h_we = 1'h1;
           if (first_block)
             begin
               if (mode)
@@ -470,15 +468,14 @@ module sha256_core(
 
       if (state_update)
         begin
-          a_new  = t1 + t2;
+          a_new  = t1_reg + t2_reg;
           b_new  = a_reg;
           c_new  = b_reg;
           d_new  = c_reg;
-          e_new  = d_reg + t1;
+          e_new  = d_reg + t1_reg;
           f_new  = e_reg;
           g_new  = f_reg;
           h_new  = g_reg;
-          a_h_we = 1'h1;
         end
     end // state_logic
 
@@ -519,6 +516,7 @@ module sha256_core(
       digest_update    = 1'h0;
       state_init       = 1'h0;
       state_update     = 1'h0;
+      a_h_we           = 1'h0;
       first_block      = 1'h0;
       ready_flag       = 1'h0;
       w_init           = 1'h0;
@@ -541,6 +539,7 @@ module sha256_core(
                 digest_init      = 1'h1;
                 w_init           = 1'h1;
                 state_init       = 1'h1;
+                a_h_we           = 1'h1;
                 first_block      = 1'h1;
                 t_ctr_rst        = 1'h1;
                 digest_valid_new = 1'h0;
@@ -553,6 +552,7 @@ module sha256_core(
               begin
                 w_init           = 1'h1;
                 state_init       = 1'h1;
+                a_h_we           = 1'h1;
                 t_ctr_rst        = 1'h1;
                 digest_valid_new = 1'h0;
                 digest_valid_we  = 1'h1;
@@ -561,8 +561,10 @@ module sha256_core(
               end
           end
 
+
         CTRL_ROUNDS0:
           begin
+            state_update    = 1'h1;
             sha256_ctrl_new = CTRL_ROUNDS1;
             sha256_ctrl_we  = 1'h1;
           end
@@ -572,6 +574,7 @@ module sha256_core(
           begin
             w_next       = 1'h1;
             state_update = 1'h1;
+            a_h_we       = 1'h1;
             t_ctr_inc    = 1'h1;
 
             if (t_ctr_reg == SHA256_ROUNDS)
-- 
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