From bbfa764f84bd2f76a011b53eaa4cd5f2178577c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 7 Nov 2014 11:56:50 +0100 Subject: Changed to asynch reset. --- src/rtl/sha256.v | 108 +++++++++++++++++++++++----------------------- src/rtl/sha256_core.v | 6 +-- src/rtl/sha256_w_mem.v | 114 ++++++++++++++++++++++++------------------------- 3 files changed, 114 insertions(+), 114 deletions(-) diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v index cd33a76..a7d3518 100644 --- a/src/rtl/sha256.v +++ b/src/rtl/sha256.v @@ -9,30 +9,30 @@ // Author: Joachim Strombergson // Copyright (c) 2014, SUNET // All rights reserved. -// -// Redistribution and use in source and binary forms, with or -// without modification, are permitted provided that the following -// conditions are met: -// -// 1. Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== @@ -41,11 +41,11 @@ module sha256( // Clock and reset. input wire clk, input wire reset_n, - + // Control. input wire cs, input wire we, - + // Data ports. input wire [7 : 0] address, input wire [31 : 0] write_data, @@ -59,7 +59,7 @@ module sha256( parameter ADDR_NAME0 = 8'h00; parameter ADDR_NAME1 = 8'h01; parameter ADDR_VERSION = 8'h02; - + parameter ADDR_CTRL = 8'h08; parameter CTRL_INIT_BIT = 0; parameter CTRL_NEXT_BIT = 1; @@ -67,7 +67,7 @@ module sha256( parameter ADDR_STATUS = 8'h09; parameter STATUS_READY_BIT = 0; parameter STATUS_VALID_BIT = 1; - + parameter ADDR_BLOCK0 = 8'h10; parameter ADDR_BLOCK1 = 8'h11; parameter ADDR_BLOCK2 = 8'h12; @@ -84,7 +84,7 @@ module sha256( parameter ADDR_BLOCK13 = 8'h1d; parameter ADDR_BLOCK14 = 8'h1e; parameter ADDR_BLOCK15 = 8'h1f; - + parameter ADDR_DIGEST0 = 8'h20; parameter ADDR_DIGEST1 = 8'h21; parameter ADDR_DIGEST2 = 8'h22; @@ -98,7 +98,7 @@ module sha256( parameter CORE_NAME1 = 32'h2d323536; // "-256" parameter CORE_VERSION = 32'h302e3830; // "0.80" - + //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- @@ -111,7 +111,7 @@ module sha256( reg next_new; reg next_we; reg next_set; - + reg ready_reg; reg [31 : 0] block0_reg; @@ -151,7 +151,7 @@ module sha256( reg digest_valid_reg; - + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- @@ -164,8 +164,8 @@ module sha256( reg [31 : 0] tmp_read_data; reg tmp_error; - - + + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- @@ -180,35 +180,35 @@ module sha256( assign read_data = tmp_read_data; assign error = tmp_error; - - + + //---------------------------------------------------------------- // core instantiation. //---------------------------------------------------------------- sha256_core core( .clk(clk), .reset_n(reset_n), - + .init(core_init), .next(core_next), - + .block(core_block), - + .ready(core_ready), - + .digest(core_digest), .digest_valid(core_digest_valid) ); - - + + //---------------------------------------------------------------- // reg_update // // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous - // active low reset. All registers have write enable. + // All registers are positive edge triggered with + // asynchronous active low reset. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin if (!reset_n) begin @@ -248,7 +248,7 @@ module sha256( begin next_reg <= next_new; end - + if (core_digest_valid) begin digest_reg <= core_digest; @@ -333,7 +333,7 @@ module sha256( begin block15_reg <= write_data; end - + end end // reg_update @@ -377,7 +377,7 @@ module sha256( //---------------------------------------------------------------- // api_logic // - // Implementation of the api logic. If cs is enabled will either + // Implementation of the api logic. If cs is enabled will either // try to write to or read from the internal registers. //---------------------------------------------------------------- always @* @@ -402,7 +402,7 @@ module sha256( block15_we = 0; tmp_read_data = 32'h00000000; tmp_error = 0; - + if (cs) begin if (we) @@ -414,7 +414,7 @@ module sha256( init_set = write_data[CTRL_INIT_BIT]; next_set = write_data[CTRL_NEXT_BIT]; end - + ADDR_BLOCK0: begin block0_we = 1; @@ -494,7 +494,7 @@ module sha256( begin block15_we = 1; end - + default: begin tmp_error = 1; @@ -515,7 +515,7 @@ module sha256( begin tmp_read_data = CORE_NAME1; end - + ADDR_VERSION: begin tmp_read_data = CORE_VERSION; @@ -525,12 +525,12 @@ module sha256( begin tmp_read_data = {28'h0000000, 2'b00, next_reg, init_reg}; end - + ADDR_STATUS: begin tmp_read_data = {28'h0000000, 2'b00, digest_valid_reg, ready_reg}; end - + ADDR_BLOCK0: begin tmp_read_data = block0_reg; @@ -650,7 +650,7 @@ module sha256( begin tmp_read_data = digest_reg[31 : 0]; end - + default: begin tmp_error = 1; diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v index d4330d9..a88a359 100644 --- a/src/rtl/sha256_core.v +++ b/src/rtl/sha256_core.v @@ -183,10 +183,10 @@ module sha256_core( //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous - // active low reset. All registers have write enable. + // All registers are positive edge triggered with + // asynchronous active low reset. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update if (!reset_n) begin diff --git a/src/rtl/sha256_w_mem.v b/src/rtl/sha256_w_mem.v index fa77c83..f58c428 100644 --- a/src/rtl/sha256_w_mem.v +++ b/src/rtl/sha256_w_mem.v @@ -8,30 +8,30 @@ // // Author: Joachim Strombergson // Copyright (c) 2014 SUNET -// -// Redistribution and use in source and binary forms, with or -// without modification, are permitted provided that the following -// conditions are met: -// -// 1. Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== @@ -47,14 +47,14 @@ module sha256_w_mem( output wire [31 : 0] w ); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- parameter CTRL_IDLE = 0; parameter CTRL_UPDATE = 1; - - + + //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- @@ -76,38 +76,38 @@ module sha256_w_mem( reg [31 : 0] w_mem14_new; reg [31 : 0] w_mem15_new; reg w_mem_we; - + reg [5 : 0] w_ctr_reg; reg [5 : 0] w_ctr_new; reg w_ctr_we; reg w_ctr_inc; reg w_ctr_rst; - + reg [1 : 0] sha256_w_mem_ctrl_reg; reg [1 : 0] sha256_w_mem_ctrl_new; reg sha256_w_mem_ctrl_we; - - + + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- reg [31 : 0] w_tmp; reg [31 : 0] w_new; - - + + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- assign w = w_tmp; - - + + //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous - // active low reset. All registers have write enable. + // All registers are positive edge triggered with + // asynchronous active low reset. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update if (!reset_n) begin @@ -151,12 +151,12 @@ module sha256_w_mem( w_mem[14] <= w_mem14_new; w_mem[15] <= w_mem15_new; end - + if (w_ctr_we) begin w_ctr_reg <= w_ctr_new; end - + if (sha256_w_mem_ctrl_we) begin sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new; @@ -164,7 +164,7 @@ module sha256_w_mem( end end // reg_update - + //---------------------------------------------------------------- // select_w // @@ -182,7 +182,7 @@ module sha256_w_mem( w_tmp = w_new; end end // select_w - + //---------------------------------------------------------------- // w_new_logic @@ -216,22 +216,22 @@ module sha256_w_mem( w_mem14_new = 32'h00000000; w_mem15_new = 32'h00000000; w_mem_we = 0; - + w_0 = w_mem[0]; w_1 = w_mem[1]; w_9 = w_mem[9]; w_14 = w_mem[14]; - d0 = {w_1[6 : 0], w_1[31 : 7]} ^ - {w_1[17 : 0], w_1[31 : 18]} ^ + d0 = {w_1[6 : 0], w_1[31 : 7]} ^ + {w_1[17 : 0], w_1[31 : 18]} ^ {3'b000, w_1[31 : 3]}; - - d1 = {w_14[16 : 0], w_14[31 : 17]} ^ - {w_14[18 : 0], w_14[31 : 19]} ^ + + d1 = {w_14[16 : 0], w_14[31 : 17]} ^ + {w_14[18 : 0], w_14[31 : 19]} ^ {10'b0000000000, w_14[31 : 10]}; - + w_new = d1 + w_9 + d0 + w_0; - + if (init) begin w_mem00_new = block[511 : 480]; @@ -273,8 +273,8 @@ module sha256_w_mem( w_mem_we = 1; end end // w_mem_update_logic - - + + //---------------------------------------------------------------- // w_ctr // W schedule adress counter. Counts from 0x10 to 0x3f and @@ -284,7 +284,7 @@ module sha256_w_mem( begin : w_ctr w_ctr_new = 0; w_ctr_we = 0; - + if (w_ctr_rst) begin w_ctr_new = 6'h00; @@ -298,7 +298,7 @@ module sha256_w_mem( end end // w_ctr - + //---------------------------------------------------------------- // sha256_w_mem_fsm // Logic for the w shedule FSM. @@ -307,10 +307,10 @@ module sha256_w_mem( begin : sha256_w_mem_fsm w_ctr_rst = 0; w_ctr_inc = 0; - + sha256_w_mem_ctrl_new = CTRL_IDLE; sha256_w_mem_ctrl_we = 0; - + case (sha256_w_mem_ctrl_reg) CTRL_IDLE: begin @@ -321,14 +321,14 @@ module sha256_w_mem( sha256_w_mem_ctrl_we = 1; end end - + CTRL_UPDATE: begin if (next) begin w_ctr_inc = 1; end - + if (w_ctr_reg == 6'h3f) begin sha256_w_mem_ctrl_new = CTRL_IDLE; -- cgit v1.2.3