core/hash/sha256 - Verilog implementation of the SHA-256 cryptographic hash function

Age	Commit message (Collapse)	Author
2016-05-31	Adding functionality to support both SHA224 and SHA256 digest modes. Note: ↵	Joachim Strömbergson
	This update changes the ADDR_CTRL API register since it adds a mode bit. The version major number has been bumped to reflect this API change. The top level testbench contains tests for SHA224 as well as old tests for SHA256. The core level tb still only tests SHA256.
2015-12-13	whack copyrights	Paul Selkirk

2015-07-17	Fixed state restore testcase in core testbench. Fixed the double block test ↵	Joachim Strömbergson
	case to really test the core. Added data valid task.
2015-07-17	Removed the address defines not needed.	Joachim Strömbergson

2015-07-17	Since state is digest having separate addresses for writing state is ↵	Joachim Strömbergson
	superflous. Captain slow.
2015-07-17	Added top level test case for restore state and continue hashing. Test OK.	Joachim Strömbergson

2015-07-16	Adding a task to dump the H state.	Joachim Strömbergson

2015-07-16	Adding test case for state restore.	Joachim Strömbergson

2015-03-31	Remove wishbone testbench code, because we no longer have the verilog.	Paul Selkirk

2014-03-16	Adding self resetting init and next flags. Updating TBs to not reset the ↵	Joachim Strömbergson
	flags. Fixing clock parameter naming.
2014-03-15	(1) Updated interface to new std. (2) Added missing input designation in ↵	Joachim Strömbergson
	tasks. Now simumaltion with ModelSim works.
2014-02-22	Updated testbenches to the new sliding window W-mem.	Joachim Strömbergson

2014-02-19	Adding a testbench for the Wishbone wrapper.	Joachim Strömbergson

2014-02-19	Adding a testbench for the SHA256 top level wrapper.	Joachim Strömbergson

2014-02-19	Adding a testbench for the SHA256 core.	Joachim Strömbergson

2014-02-19	Adding a testbench for the w memory module.	Joachim Strömbergson