core/hash/sha256 - Verilog implementation of the SHA-256 cryptographic hash function

Age	Commit message (Collapse)	Author
2015-07-17	Since state is digest having separate addresses for writing state is ↵	Joachim Strömbergson
	superflous. Captain slow.
2015-07-16	Added logic to write state into the state registers. Simplified the state ↵	Joachim Strömbergson
	write interface to a common data port.
2015-07-16	The digest is the complete state so we only need to be able to write back ↵	Joachim Strömbergson
	state. The state addresses are still readable though.
2015-07-16	(1) Adding addresses to be able to read and write the internal hash state ↵	Joachim Strömbergson
	from the API. (2) Bumped version to reflect the changes to the API. (3) Added ports for state access in the core module and connected them in the top level wrapper.
2015-03-31	Revert streamlined wrapper, and don't delay register reads.	Paul Selkirk

2015-03-17	Rearrange cores.	Paul Selkirk

2014-11-07	Changed to asynch reset.	Joachim Strömbergson

2014-03-17	Removed redundant flag reset wires.	Joachim Strömbergson

2014-03-16	Adding self resetting init and next flags. Updating TBs to not reset the ↵	Joachim Strömbergson
	flags. Fixing clock parameter naming.
2014-03-15	(1) Updated interface to new std. (2) Added missing input designation in ↵	Joachim Strömbergson
	tasks. Now simumaltion with ModelSim works.
2014-02-19	Adding top level wrapper for the sha256. This wrapper provides a simple ↵	Joachim Strömbergson
	memory like interface.