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-rw-r--r--src/tb/tb_sha256_core.v307
1 files changed, 218 insertions, 89 deletions
diff --git a/src/tb/tb_sha256_core.v b/src/tb/tb_sha256_core.v
index df0cafc..5fef6cf 100644
--- a/src/tb/tb_sha256_core.v
+++ b/src/tb/tb_sha256_core.v
@@ -8,30 +8,30 @@
// Author: Joachim Strombergson
// Copyright (c) 2014, SUNET
// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -46,7 +46,7 @@
// Test module.
//------------------------------------------------------------------
module tb_sha256_core();
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -54,8 +54,8 @@ module tb_sha256_core();
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
-
-
+
+
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
@@ -68,41 +68,60 @@ module tb_sha256_core();
reg tb_init;
reg tb_next;
reg [511 : 0] tb_block;
+ reg [31 : 0] tb_state_wr_data;
+ reg tb_state0_we;
+ reg tb_state1_we;
+ reg tb_state2_we;
+ reg tb_state3_we;
+ reg tb_state4_we;
+ reg tb_state5_we;
+ reg tb_state6_we;
+ reg tb_state7_we;
wire tb_ready;
wire [255 : 0] tb_digest;
wire tb_digest_valid;
-
-
+
+
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha256_core dut(
- .clk(tb_clk),
- .reset_n(tb_reset_n),
-
- .init(tb_init),
- .next(tb_next),
-
- .block(tb_block),
-
- .ready(tb_ready),
-
- .digest(tb_digest),
- .digest_valid(tb_digest_valid)
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+
+ .init(tb_init),
+ .next(tb_next),
+
+ .block(tb_block),
+
+ .state_wr_data(tb_state_wr_data),
+ .state0_we(tb_state0_we),
+ .state1_we(tb_state1_we),
+ .state2_we(tb_state2_we),
+ .state3_we(tb_state3_we),
+ .state4_we(tb_state4_we),
+ .state5_we(tb_state5_we),
+ .state6_we(tb_state6_we),
+ .state7_we(tb_state7_we),
+
+ .ready(tb_ready),
+
+ .digest(tb_digest),
+ .digest_valid(tb_digest_valid)
);
-
+
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
- always
+ always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
-
+
//----------------------------------------------------------------
// sys_monitor()
@@ -120,7 +139,7 @@ module tb_sha256_core();
end
end
-
+
//----------------------------------------------------------------
// dump_dut_state()
//
@@ -131,40 +150,40 @@ module tb_sha256_core();
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
- $display("init = 0x%01x, next = 0x%01x",
+ $display("init = 0x%01x, next = 0x%01x",
dut.init, dut.next);
$display("block = 0x%0128x", dut.block);
- $display("ready = 0x%01x, valid = 0x%01x",
+ $display("ready = 0x%01x, valid = 0x%01x",
dut.ready, dut.digest_valid);
$display("digest = 0x%064x", dut.digest);
- $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
+ $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg);
- $display("H4_reg = 0x%08x, H5_reg = 0x%08x, H6_reg = 0x%08x, H7_reg = 0x%08x",
+ $display("H4_reg = 0x%08x, H5_reg = 0x%08x, H6_reg = 0x%08x, H7_reg = 0x%08x",
dut.H4_reg, dut.H5_reg, dut.H6_reg, dut.H7_reg);
$display("");
-
+
$display("Control signals and counter:");
$display("sha256_ctrl_reg = 0x%02x", dut.sha256_ctrl_reg);
- $display("digest_init = 0x%01x, digest_update = 0x%01x",
+ $display("digest_init = 0x%01x, digest_update = 0x%01x",
dut.digest_init, dut.digest_update);
- $display("state_init = 0x%01x, state_update = 0x%01x",
+ $display("state_init = 0x%01x, state_update = 0x%01x",
dut.state_init, dut.state_update);
- $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
+ $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
dut.first_block, dut.ready_flag, dut.w_init);
- $display("t_ctr_inc = 0x%01x, t_ctr_rst = 0x%01x, t_ctr_reg = 0x%02x",
+ $display("t_ctr_inc = 0x%01x, t_ctr_rst = 0x%01x, t_ctr_reg = 0x%02x",
dut.t_ctr_inc, dut.t_ctr_rst, dut.t_ctr_reg);
$display("");
$display("State registers:");
- $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x",
+ $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x",
dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg);
- $display("e_reg = 0x%08x, f_reg = 0x%08x, g_reg = 0x%08x, h_reg = 0x%08x",
+ $display("e_reg = 0x%08x, f_reg = 0x%08x, g_reg = 0x%08x, h_reg = 0x%08x",
dut.e_reg, dut.f_reg, dut.g_reg, dut.h_reg);
$display("");
- $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x",
+ $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x",
dut.a_new, dut.b_new, dut.c_new, dut.d_new);
- $display("e_new = 0x%08x, f_new = 0x%08x, g_new = 0x%08x, h_new = 0x%08x",
+ $display("e_new = 0x%08x, f_new = 0x%08x, g_new = 0x%08x, h_new = 0x%08x",
dut.e_new, dut.f_new, dut.g_new, dut.h_new);
$display("");
@@ -174,8 +193,8 @@ module tb_sha256_core();
$display("");
end
endtask // dump_dut_state
-
-
+
+
//----------------------------------------------------------------
// reset_dut()
//
@@ -190,7 +209,7 @@ module tb_sha256_core();
end
endtask // reset_dut
-
+
//----------------------------------------------------------------
// init_sim()
//
@@ -199,20 +218,29 @@ module tb_sha256_core();
//----------------------------------------------------------------
task init_sim();
begin
- cycle_ctr = 0;
- error_ctr = 0;
- tc_ctr = 0;
-
- tb_clk = 0;
- tb_reset_n = 1;
+ cycle_ctr = 0;
+ error_ctr = 0;
+ tc_ctr = 0;
+
+ tb_clk = 0;
+ tb_reset_n = 1;
- tb_init = 0;
- tb_next = 0;
- tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ tb_init = 0;
+ tb_next = 0;
+ tb_block = 512'h0;
+ tb_state_wr_data = 32'h0;
+ tb_state0_we = 0;
+ tb_state1_we = 0;
+ tb_state2_we = 0;
+ tb_state3_we = 0;
+ tb_state4_we = 0;
+ tb_state5_we = 0;
+ tb_state6_we = 0;
+ tb_state7_we = 0;
end
endtask // init_dut
-
+
//----------------------------------------------------------------
// display_test_result()
//
@@ -230,7 +258,7 @@ module tb_sha256_core();
end
end
endtask // display_test_result
-
+
//----------------------------------------------------------------
// wait_ready()
@@ -250,7 +278,7 @@ module tb_sha256_core();
end
endtask // wait_ready
-
+
//----------------------------------------------------------------
// single_block_test()
//
@@ -268,25 +296,25 @@ module tb_sha256_core();
#(CLK_PERIOD);
wait_ready();
-
+
if (tb_digest == expected)
begin
$display("*** TC %0d successful.", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d NOT successful.", tc_number);
$display("Expected: 0x%064x", expected);
$display("Got: 0x%064x", tb_digest);
$display("");
-
+
error_ctr = error_ctr + 1;
end
end
endtask // single_block_test
-
+
//----------------------------------------------------------------
// double_block_test()
//
@@ -313,19 +341,19 @@ module tb_sha256_core();
wait_ready();
db_digest1 = tb_digest;
$display("*** TC %0d first block done.", tc_number);
-
+
$display("*** TC %0d second block started.", tc_number);
tb_block = block2;
tb_next = 1;
#(CLK_PERIOD);
wait_ready();
$display("*** TC %0d second block done.", tc_number);
-
+
if (db_digest1 == expected1)
begin
$display("*** TC %0d first block successful", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d first block NOT successful", tc_number);
@@ -334,12 +362,12 @@ module tb_sha256_core();
$display("");
db_error = 1;
end
-
+
if (db_digest1 == expected1)
begin
$display("*** TC %0d second block successful", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d second block NOT successful", tc_number);
@@ -354,12 +382,104 @@ module tb_sha256_core();
error_ctr = error_ctr + 1;
end
end
- endtask // single_block_test
-
-
+ endtask // double_block_test
+
+
+ //----------------------------------------------------------------
+ // state_restore_test()
+ //
+ // Run a test where the state for the first block is written
+ // to the core and then a second block is processed. The result
+ // should match the dual block test.
+ //----------------------------------------------------------------
+ task state_restore_test(input [7 : 0] tc_number,
+ input [255 : 0] state,
+ input [511 : 0] block,
+ input [255 : 0] expected);
+
+ reg [255 : 0] db_digest1;
+ reg db_error;
+ begin
+ $display("*** TC %0d state restore block test case started.", tc_number);
+ db_error = 0;
+ tc_ctr = tc_ctr + 1;
+
+ $display("*** TC %0d Writing state to core.", tc_number);
+
+ tb_state_wr_data = state[255 : 224];
+ tb_state0_we = 1;
+ #(CLK_PERIOD);
+ tb_state0_we = 0;
+
+ tb_state_wr_data = state[223 : 192];
+ tb_state1_we = 1;
+ #(CLK_PERIOD);
+ tb_state1_we = 0;
+
+ tb_state_wr_data = state[191 : 160];
+ tb_state2_we = 1;
+ #(CLK_PERIOD);
+ tb_state2_we = 0;
+
+ tb_state_wr_data = state[159 : 128];
+ tb_state3_we = 1;
+ #(CLK_PERIOD);
+ tb_state3_we = 0;
+
+ tb_state_wr_data = state[127 : 096];
+ tb_state4_we = 1;
+ #(CLK_PERIOD);
+ tb_state4_we = 0;
+
+ tb_state_wr_data = state[095 : 0064];
+ tb_state5_we = 1;
+ #(CLK_PERIOD);
+ tb_state5_we = 0;
+
+ tb_state_wr_data = state[063 : 0032];
+ tb_state6_we = 1;
+ #(CLK_PERIOD);
+ tb_state6_we = 0;
+
+ tb_state_wr_data = state[031 : 000];
+ tb_state7_we = 1;
+ #(CLK_PERIOD);
+ tb_state7_we = 0;
+
+ #(CLK_PERIOD);
+
+ $display("*** TC %0d block started.", tc_number);
+ tb_block = block;
+ tb_next = 1;
+ #(CLK_PERIOD);
+ wait_ready();
+ $display("*** TC %0d block done.", tc_number);
+
+ if (db_digest1 == expected)
+ begin
+ $display("*** TC %0d block successful", tc_number);
+ $display("");
+ end
+ else
+ begin
+ $display("*** ERROR: TC %0d block NOT successful", tc_number);
+ $display("Expected: 0x%064x", expected);
+ $display("Got: 0x%064x", tb_digest);
+ $display("");
+ db_error = 1;
+ end
+
+ if (db_error)
+ begin
+ error_ctr = error_ctr + 1;
+ end
+ end
+ endtask // state_restore_test
+
+
//----------------------------------------------------------------
// sha256_core_test
- // The main test functionality.
+ // The main test functionality.
//
// Test cases taken from:
// http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA256.pdf
@@ -373,14 +493,18 @@ module tb_sha256_core();
reg [255 : 0] res2_1;
reg [511 : 0] tc2_2;
reg [255 : 0] res2_2;
-
+
+ reg [255 : 0] tc3_state;
+ reg [511 : 0] tc3_block;
+ reg [255 : 0] tc3_res;
+
$display(" -- Testbench for sha256 core started --");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
-
+
// TC1: Single block message: "abc".
tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
res1 = 256'hBA7816BF8F01CFEA414140DE5DAE2223B00361A396177A9CB410FF61F20015AD;
@@ -390,11 +514,16 @@ module tb_sha256_core();
// "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
res2_1 = 256'h85E655D6417A17953363376A624CDE5C76E09589CAC5F811CC4B32C1F20E533A;
-
+
tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
res2_2 = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
double_block_test(2, tc2_1, res2_1, tc2_2, res2_2);
-
+
+ tc3_state = 256'h85E655D6417A17953363376A624CDE5C76E09589CAC5F811CC4B32C1F20E533A;
+ tc3_block = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
+ tc3_res = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
+ state_restore_test(3, tc3_state, tc3_block, tc3_res);
+
display_test_result();
$display("*** Simulation done.");
$finish;
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