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-rw-r--r--src/rtl/sha256_w_mem.v113
1 files changed, 19 insertions, 94 deletions
diff --git a/src/rtl/sha256_w_mem.v b/src/rtl/sha256_w_mem.v
index 501cef0..fef1205 100644
--- a/src/rtl/sha256_w_mem.v
+++ b/src/rtl/sha256_w_mem.v
@@ -51,13 +51,6 @@ module sha256_w_mem(
//----------------------------------------------------------------
- // Internal constant and parameter definitions.
- //----------------------------------------------------------------
- parameter CTRL_IDLE = 0;
- parameter CTRL_UPDATE = 1;
-
-
- //----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
@@ -82,12 +75,6 @@ module sha256_w_mem(
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
- reg w_ctr_inc;
- reg w_ctr_rst;
-
- reg [1 : 0] sha256_w_mem_ctrl_reg;
- reg [1 : 0] sha256_w_mem_ctrl_new;
- reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
@@ -111,26 +98,14 @@ module sha256_w_mem(
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
+ integer i;
+
if (!reset_n)
begin
- w_mem[00] <= 32'h00000000;
- w_mem[01] <= 32'h00000000;
- w_mem[02] <= 32'h00000000;
- w_mem[03] <= 32'h00000000;
- w_mem[04] <= 32'h00000000;
- w_mem[05] <= 32'h00000000;
- w_mem[06] <= 32'h00000000;
- w_mem[07] <= 32'h00000000;
- w_mem[08] <= 32'h00000000;
- w_mem[09] <= 32'h00000000;
- w_mem[10] <= 32'h00000000;
- w_mem[11] <= 32'h00000000;
- w_mem[12] <= 32'h00000000;
- w_mem[13] <= 32'h00000000;
- w_mem[14] <= 32'h00000000;
- w_mem[15] <= 32'h00000000;
- w_ctr_reg <= 6'h00;
- sha256_w_mem_ctrl_reg <= CTRL_IDLE;
+ for (i = 0 ; i < 16 ; i = i + 1)
+ w_mem[i] <= 32'h0;
+
+ w_ctr_reg <= 6'h0;
end
else
begin
@@ -155,14 +130,7 @@ module sha256_w_mem(
end
if (w_ctr_we)
- begin
- w_ctr_reg <= w_ctr_new;
- end
-
- if (sha256_w_mem_ctrl_we)
- begin
- sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
- end
+ w_ctr_reg <= w_ctr_new;
end
end // reg_update
@@ -176,13 +144,9 @@ module sha256_w_mem(
always @*
begin : select_w
if (w_ctr_reg < 16)
- begin
- w_tmp = w_mem[w_ctr_reg[3 : 0]];
- end
+ w_tmp = w_mem[w_ctr_reg[3 : 0]];
else
- begin
- w_tmp = w_new;
- end
+ w_tmp = w_new;
end // select_w
@@ -254,7 +218,8 @@ module sha256_w_mem(
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
- else if (w_ctr_reg > 15)
+
+ if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
@@ -284,62 +249,22 @@ module sha256_w_mem(
//----------------------------------------------------------------
always @*
begin : w_ctr
- w_ctr_new = 0;
- w_ctr_we = 0;
+ w_ctr_new = 6'h0;
+ w_ctr_we = 1'h0;
- if (w_ctr_rst)
+ if (init)
begin
- w_ctr_new = 6'h00;
- w_ctr_we = 1;
+ w_ctr_new = 6'h0;
+ w_ctr_we = 1'h1;
end
- if (w_ctr_inc)
+ if (next)
begin
- w_ctr_new = w_ctr_reg + 6'h01;
- w_ctr_we = 1;
+ w_ctr_new = w_ctr_reg + 6'h1;
+ w_ctr_we = 1'h1;
end
end // w_ctr
-
- //----------------------------------------------------------------
- // sha256_w_mem_fsm
- // Logic for the w shedule FSM.
- //----------------------------------------------------------------
- always @*
- begin : sha256_w_mem_fsm
- w_ctr_rst = 0;
- w_ctr_inc = 0;
-
- sha256_w_mem_ctrl_new = CTRL_IDLE;
- sha256_w_mem_ctrl_we = 0;
-
- case (sha256_w_mem_ctrl_reg)
- CTRL_IDLE:
- begin
- if (init)
- begin
- w_ctr_rst = 1;
- sha256_w_mem_ctrl_new = CTRL_UPDATE;
- sha256_w_mem_ctrl_we = 1;
- end
- end
-
- CTRL_UPDATE:
- begin
- if (next)
- begin
- w_ctr_inc = 1;
- end
-
- if (w_ctr_reg == 6'h3f)
- begin
- sha256_w_mem_ctrl_new = CTRL_IDLE;
- sha256_w_mem_ctrl_we = 1;
- end
- end
- endcase // case (sha256_ctrl_reg)
- end // sha256_ctrl_fsm
-
endmodule // sha256_w_mem
//======================================================================