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-rw-r--r--src/rtl/sha256_w_mem.v114
1 files changed, 57 insertions, 57 deletions
diff --git a/src/rtl/sha256_w_mem.v b/src/rtl/sha256_w_mem.v
index fa77c83..f58c428 100644
--- a/src/rtl/sha256_w_mem.v
+++ b/src/rtl/sha256_w_mem.v
@@ -8,30 +8,30 @@
//
// Author: Joachim Strombergson
// Copyright (c) 2014 SUNET
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -47,14 +47,14 @@ module sha256_w_mem(
output wire [31 : 0] w
);
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
-
-
+
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
@@ -76,38 +76,38 @@ module sha256_w_mem(
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
-
+
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
-
+
reg [1 : 0] sha256_w_mem_ctrl_reg;
reg [1 : 0] sha256_w_mem_ctrl_new;
reg sha256_w_mem_ctrl_we;
-
-
+
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
-
-
+
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
-
-
+
+
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
- // active low reset. All registers have write enable.
+ // All registers are positive edge triggered with
+ // asynchronous active low reset.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
@@ -151,12 +151,12 @@ module sha256_w_mem(
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
-
+
if (w_ctr_we)
begin
w_ctr_reg <= w_ctr_new;
end
-
+
if (sha256_w_mem_ctrl_we)
begin
sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
@@ -164,7 +164,7 @@ module sha256_w_mem(
end
end // reg_update
-
+
//----------------------------------------------------------------
// select_w
//
@@ -182,7 +182,7 @@ module sha256_w_mem(
w_tmp = w_new;
end
end // select_w
-
+
//----------------------------------------------------------------
// w_new_logic
@@ -216,22 +216,22 @@ module sha256_w_mem(
w_mem14_new = 32'h00000000;
w_mem15_new = 32'h00000000;
w_mem_we = 0;
-
+
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
- d0 = {w_1[6 : 0], w_1[31 : 7]} ^
- {w_1[17 : 0], w_1[31 : 18]} ^
+ d0 = {w_1[6 : 0], w_1[31 : 7]} ^
+ {w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
-
- d1 = {w_14[16 : 0], w_14[31 : 17]} ^
- {w_14[18 : 0], w_14[31 : 19]} ^
+
+ d1 = {w_14[16 : 0], w_14[31 : 17]} ^
+ {w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
-
+
w_new = d1 + w_9 + d0 + w_0;
-
+
if (init)
begin
w_mem00_new = block[511 : 480];
@@ -273,8 +273,8 @@ module sha256_w_mem(
w_mem_we = 1;
end
end // w_mem_update_logic
-
-
+
+
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
@@ -284,7 +284,7 @@ module sha256_w_mem(
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
-
+
if (w_ctr_rst)
begin
w_ctr_new = 6'h00;
@@ -298,7 +298,7 @@ module sha256_w_mem(
end
end // w_ctr
-
+
//----------------------------------------------------------------
// sha256_w_mem_fsm
// Logic for the w shedule FSM.
@@ -307,10 +307,10 @@ module sha256_w_mem(
begin : sha256_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
-
+
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 0;
-
+
case (sha256_w_mem_ctrl_reg)
CTRL_IDLE:
begin
@@ -321,14 +321,14 @@ module sha256_w_mem(
sha256_w_mem_ctrl_we = 1;
end
end
-
+
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
-
+
if (w_ctr_reg == 6'h3f)
begin
sha256_w_mem_ctrl_new = CTRL_IDLE;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-14 06:37:22 +0000