Connected the pipeline regs for t1 and t2 in the stat update logic. Verified functionality. Updated README after test implementation. The design now meets 100 MHz clock in Artix7 with speed grade -1.

1 files changed, 2 insertions, 1 deletions

diff --git a/src/tb/tb_sha256_core.v b/src/tb/tb_sha256_core.v
index 3b76aca..a037128 100644
--- a/src/tb/tb_sha256_core.v
+++ b/src/tb/tb_sha256_core.v
@@ -186,7 +186,8 @@ module tb_sha256_core();
 
       $display("State update values:");
       $display("w  = 0x%08x, k  = 0x%08x", dut.w_data, dut.k_data);
-      $display("t1 = 0x%08x, t2 = 0x%08x", dut.t1, dut.t2);
+      $display("t1_new = 0x%08x, t1_reg = 0x%08x, t2_new = 0x%08x, t2_reg = 0x%08x",
+               dut.t1_new, dut.t1_reg, dut.t2_new, dut.t2_reg);
       $display("");
     end
   endtask // dump_dut_state