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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-07-16 17:07:31 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-07-16 17:07:31 +0200 |
| commit | 2233de15379a0ba4abf450252bd570446ed1f6eb (patch) | |
| tree | a7249429893c5993cbbc4ddb7ea5ecff8590c78f /src/rtl/sha256_core.v | |
| parent | ce56b11187b92572193fa9327841ad2ef2e792f8 (diff) | |
(1) Adding addresses to be able to read and write the internal hash state from the API. (2) Bumped version to reflect the changes to the API. (3) Added ports for state access in the core module and connected them in the top level wrapper.
Diffstat (limited to 'src/rtl/sha256_core.v')
| -rw-r--r-- | src/rtl/sha256_core.v | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v index a88a359..dbcec3b 100644 --- a/src/rtl/sha256_core.v +++ b/src/rtl/sha256_core.v @@ -45,6 +45,39 @@ module sha256_core( input wire [511 : 0] block, + // State access ports + input wire [31 : 0] H0_wr_data, + input wire H0_we, + output wire [31 : 0] H0_rd_data, + + input wire [31 : 0] H1_wr_data, + input wire H1_we, + output wire [31 : 0] H1_rd_data, + + input wire [31 : 0] H2_wr_data, + input wire H2_we, + output wire [31 : 0] H2_rd_data, + + input wire [31 : 0] H3_wr_data, + input wire H3_we, + output wire [31 : 0] H3_rd_data, + + input wire [31 : 0] H4_wr_data, + input wire H4_we, + output wire [31 : 0] H4_rd_data, + + input wire [31 : 0] H5_wr_data, + input wire H5_we, + output wire [31 : 0] H5_rd_data, + + input wire [31 : 0] H6_wr_data, + input wire H6_we, + output wire [31 : 0] H6_rd_data, + + input wire [31 : 0] H7_wr_data, + input wire H7_we, + output wire [31 : 0] H7_rd_data, + output wire ready, output wire [255 : 0] digest, |