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core/hash/sha256
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Verilog implementation of the SHA-256 cryptographic hash function
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master
Ported the timing fix from SHA-512 to SHA-256. The core can now run at 170 MH...
Joachim Strömbergson
6 years
Age
Commit message
Author
2019-01-08
Ported the timing fix from SHA-512 to SHA-256. The core can now run at 170 MH...
HEAD
master
Joachim Strömbergson
2018-10-18
Compacted the code for K constants.
Joachim Strömbergson
2018-10-18
(1) Locked down API to ignore read or write requests that could leak info or ...
Joachim Strömbergson
2018-10-16
Added width definition.
Joachim Strömbergson
2018-08-28
Connected the pipeline regs for t1 and t2 in the stat update logic. Verified ...
Joachim Strömbergson
2018-08-28
Added pipeline register and stall cycle in the FSM to accomodate the pipeline...
Joachim Strömbergson
2018-04-27
Removed FSM and cleaned up code in W mem. Cleaned up testbenches to silence w...
Joachim Strömbergson
2018-04-27
Updated Makefile with flags for cc. Added support for linting.
Joachim Strömbergson
2016-05-31
Updated README with status info, note about the new SHA224 functionality and ...
Joachim Strömbergson
2016-05-31
Adding functionality to support both SHA224 and SHA256 digest modes. Note: Th...
Joachim Strömbergson
[...]
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