From 9daf474ac53397fbe8c427493f619b89917fc8fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Wed, 3 Oct 2018 11:28:18 +0200 Subject: Restricted write access for control bits to when the core is ready. --- src/rtl/sha1.v | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v index 9a112b0..c1fd8ec 100644 --- a/src/rtl/sha1.v +++ b/src/rtl/sha1.v @@ -195,13 +195,16 @@ module sha1( begin if (we) begin - if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) - block_we = 1; - - if (address == ADDR_CTRL) + if (core_ready) begin - init_new = write_data[CTRL_INIT_BIT]; - next_new = write_data[CTRL_NEXT_BIT]; + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) + block_we = 1; + + if (address == ADDR_CTRL) + begin + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + end end end // if (write_read) else @@ -210,7 +213,8 @@ module sha1( tmp_read_data = block_reg[address[3 : 0]]; if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4)) - tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32]; + if (core_ready) + tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32]; case (address) // Read operations. -- cgit v1.2.3