From 7527ad5bb6dc560a235398439863a6ee785ad2a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 8 Dec 2017 10:01:27 +0100 Subject: Syncecd SHA-1 core to github repo. No functional changes, but more compact code and a lot of minor fixes to silence warnings. --- src/tb/tb_sha1.v | 164 ++++++++++++++++++++++++------------------------- src/tb/tb_sha1_core.v | 118 +++++++++++++++++------------------ src/tb/tb_sha1_w_mem.v | 23 +++---- 3 files changed, 146 insertions(+), 159 deletions(-) (limited to 'src/tb') diff --git a/src/tb/tb_sha1.v b/src/tb/tb_sha1.v index 9c339a0..f454034 100644 --- a/src/tb/tb_sha1.v +++ b/src/tb/tb_sha1.v @@ -8,7 +8,7 @@ // Author: Joachim Strombergson // Copyright (c) 2014, NORDUnet A/S // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -37,13 +37,8 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - module tb_sha1(); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -52,7 +47,7 @@ module tb_sha1(); parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = CLK_HALF_PERIOD * 2; - + parameter ADDR_NAME0 = 8'h00; parameter ADDR_NAME1 = 8'h01; parameter ADDR_VERSION = 8'h02; @@ -66,7 +61,7 @@ module tb_sha1(); parameter ADDR_STATUS = 8'h09; parameter STATUS_READY_BIT = 0; parameter STATUS_VALID_BIT = 1; - + parameter ADDR_BLOCK0 = 8'h10; parameter ADDR_BLOCK1 = 8'h11; parameter ADDR_BLOCK2 = 8'h12; @@ -83,14 +78,14 @@ module tb_sha1(); parameter ADDR_BLOCK13 = 8'h1d; parameter ADDR_BLOCK14 = 8'h1e; parameter ADDR_BLOCK15 = 8'h1f; - + parameter ADDR_DIGEST0 = 8'h20; parameter ADDR_DIGEST1 = 8'h21; parameter ADDR_DIGEST2 = 8'h22; parameter ADDR_DIGEST3 = 8'h23; parameter ADDR_DIGEST4 = 8'h24; - + //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- @@ -108,35 +103,35 @@ module tb_sha1(); reg [31 : 0] read_data; reg [159 : 0] digest_data; - - + + //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- sha1 dut( .clk(tb_clk), .reset_n(tb_reset_n), - + .cs(tb_cs), .we(tb_write_read), - + .address(tb_address), .write_data(tb_data_in), .read_data(tb_data_out), - .error(tb_error) + .error(tb_error) ); - + //---------------------------------------------------------------- // clk_gen // - // Clock generator process. + // Clock generator process. //---------------------------------------------------------------- - always + always begin : clk_gen #CLK_HALF_PERIOD tb_clk = !tb_clk; end // clk_gen - + //---------------------------------------------------------------- // sys_monitor @@ -147,7 +142,7 @@ module tb_sha1(); begin dump_core_state(); end - + if (DEBUG_TOP) begin dump_top_state(); @@ -157,13 +152,13 @@ module tb_sha1(); cycle_ctr = cycle_ctr + 1; end - + //---------------------------------------------------------------- // dump_top_state() // // Dump state of the the top of the dut. //---------------------------------------------------------------- - task dump_top_state(); + task dump_top_state; begin $display("State of top"); $display("-------------"); @@ -172,24 +167,21 @@ module tb_sha1(); $display("address = 0x%02x, write_data = 0x%08x", dut.address, dut.write_data); $display("error = 0x%01x, read_data = 0x%08x", dut.error, dut.read_data); $display(""); - + $display("Control and status flags:"); - $display("init = 0x%01x, next = 0x%01x, ready = 0x%01x", + $display("init = 0x%01x, next = 0x%01x, ready = 0x%01x", dut.init_reg, dut.next_reg, dut.ready_reg); $display(""); $display("block registers:"); - $display("block0_reg = 0x%08x, block1_reg = 0x%08x, block2_reg = 0x%08x, block3_reg = 0x%08x", - dut.block0_reg, dut.block1_reg, dut.block2_reg, dut.block3_reg); - - $display("block4_reg = 0x%08x, block5_reg = 0x%08x, block6_reg = 0x%08x, block7_reg = 0x%08x", - dut.block4_reg, dut.block5_reg, dut.block6_reg, dut.block7_reg); - - $display("block8_reg = 0x%08x, block9_reg = 0x%08x, block10_reg = 0x%08x, block11_reg = 0x%08x", - dut.block8_reg, dut.block9_reg, dut.block10_reg, dut.block11_reg); - - $display("block12_reg = 0x%08x, block13_reg = 0x%08x, block14_reg = 0x%08x, block15_reg = 0x%08x", - dut.block12_reg, dut.block13_reg, dut.block14_reg, dut.block15_reg); + $display("block0 = 0x%08x, block1 = 0x%08x, block2 = 0x%08x, block3 = 0x%08x", + dut.block_reg[00], dut.block_reg[01], dut.block_reg[02], dut.block_reg[03]); + $display("block4 = 0x%08x, block5 = 0x%08x, block6 = 0x%08x, block7 = 0x%08x", + dut.block_reg[04], dut.block_reg[05], dut.block_reg[06], dut.block_reg[07]); + $display("block8 = 0x%08x, block9 = 0x%08x, block10 = 0x%08x, block11 = 0x%08x", + dut.block_reg[08], dut.block_reg[09], dut.block_reg[10], dut.block_reg[11]); + $display("block12 = 0x%08x, block13 = 0x%08x, block14 = 0x%08x, block15 = 0x%08x", + dut.block_reg[12], dut.block_reg[13], dut.block_reg[14], dut.block_reg[15]); $display(""); $display("Digest registers:"); @@ -198,59 +190,59 @@ module tb_sha1(); end endtask // dump_top_state - + //---------------------------------------------------------------- // dump_core_state() // // Dump the state of the core inside the dut. //---------------------------------------------------------------- - task dump_core_state(); + task dump_core_state; begin $display("State of core"); $display("-------------"); $display("Inputs and outputs:"); - $display("init = 0x%01x, next = 0x%01x", + $display("init = 0x%01x, next = 0x%01x", dut.core.init, dut.core.next); $display("block = 0x%0128x", dut.core.block); - $display("ready = 0x%01x, valid = 0x%01x", + $display("ready = 0x%01x, valid = 0x%01x", dut.core.ready, dut.core.digest_valid); $display("digest = 0x%040x", dut.core.digest); - $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", + $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", dut.core.H0_reg, dut.core.H1_reg, dut.core.H2_reg, dut.core.H3_reg, dut.core.H4_reg); $display(""); - + $display("Control signals and counter:"); $display("sha1_ctrl_reg = 0x%01x", dut.core.sha1_ctrl_reg); - $display("digest_init = 0x%01x, digest_update = 0x%01x", + $display("digest_init = 0x%01x, digest_update = 0x%01x", dut.core.digest_init, dut.core.digest_update); - $display("state_init = 0x%01x, state_update = 0x%01x", + $display("state_init = 0x%01x, state_update = 0x%01x", dut.core.state_init, dut.core.state_update); - $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", + $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", dut.core.first_block, dut.core.ready_flag, dut.core.w_init); - $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", + $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", dut.core.round_ctr_inc, dut.core.round_ctr_rst, dut.core.round_ctr_reg); $display(""); $display("State registers:"); - $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", + $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", dut.core.a_reg, dut.core.b_reg, dut.core.c_reg, dut.core.d_reg, dut.core.e_reg); - $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", + $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", dut.core.a_new, dut.core.b_new, dut.core.c_new, dut.core.d_new, dut.core.e_new); $display(""); $display("State update values:"); - $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", + $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", dut.core.state_logic.f, dut.core.state_logic.k, dut.core.state_logic.t, dut.core.w); $display(""); end endtask // dump_core_state - - + + //---------------------------------------------------------------- // reset_dut() //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -259,19 +251,19 @@ module tb_sha1(); end endtask // reset_dut - + //---------------------------------------------------------------- // init_sim() // // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 32'h00000000; error_ctr = 32'h00000000; tc_ctr = 32'h00000000; - + tb_clk = 0; tb_reset_n = 0; tb_cs = 0; @@ -281,13 +273,13 @@ module tb_sha1(); end endtask // init_dut - + //---------------------------------------------------------------- // display_test_result() // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_result(); + task display_test_result; begin if (error_ctr == 0) begin @@ -300,8 +292,8 @@ module tb_sha1(); end end endtask // display_test_result - - + + //---------------------------------------------------------------- // wait_ready() // @@ -312,17 +304,17 @@ module tb_sha1(); // when the dut is actively processing and will in fact at some // point set the flag. //---------------------------------------------------------------- - task wait_ready(); + task wait_ready; begin read_data = 0; - + while (read_data == 0) begin read_word(ADDR_STATUS); end end endtask // wait_ready - + //---------------------------------------------------------------- // read_word() @@ -347,7 +339,7 @@ module tb_sha1(); end end endtask // read_word - + //---------------------------------------------------------------- // write_word() @@ -362,7 +354,7 @@ module tb_sha1(); $display("*** Writing 0x%08x to 0x%02x.", word, address); $display(""); end - + tb_address = address; tb_data_in = word; tb_cs = 1; @@ -373,7 +365,7 @@ module tb_sha1(); end endtask // write_word - + //---------------------------------------------------------------- // write_block() // @@ -400,13 +392,13 @@ module tb_sha1(); end endtask // write_block - + //---------------------------------------------------------------- // check_name_version() // // Read the name and version from the DUT. //---------------------------------------------------------------- - task check_name_version(); + task check_name_version; reg [31 : 0] name0; reg [31 : 0] name1; reg [31 : 0] version; @@ -426,7 +418,7 @@ module tb_sha1(); version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]); end endtask // check_name_version - + //---------------------------------------------------------------- // read_digest() @@ -434,7 +426,7 @@ module tb_sha1(); // Read the digest in the dut. The resulting digest will be // available in the global variable digest_data. //---------------------------------------------------------------- - task read_digest(); + task read_digest; begin read_word(ADDR_DIGEST0); digest_data[159 : 128] = read_data; @@ -448,8 +440,8 @@ module tb_sha1(); digest_data[31 : 0] = read_data; end endtask // read_digest - - + + //---------------------------------------------------------------- // single_block_test() // @@ -460,8 +452,8 @@ module tb_sha1(); input [159 : 0] expected ); begin - $display("*** TC%01d - Single block test started.", tc_ctr); - + $display("*** TC%01d - Single block test started.", tc_ctr); + write_block(block); write_word(ADDR_CTRL, CTRL_INIT_VALUE); #(CLK_PERIOD); @@ -479,12 +471,12 @@ module tb_sha1(); $display("TC%01d: Got: 0x%040x", tc_ctr, digest_data); error_ctr = error_ctr + 1; end - $display("*** TC%01d - Single block test done.", tc_ctr); + $display("*** TC%01d - Single block test done.", tc_ctr); tc_ctr = tc_ctr + 1; end endtask // single_block_test - - + + //---------------------------------------------------------------- // double_block_test() // @@ -498,7 +490,7 @@ module tb_sha1(); input [159 : 0] expected1 ); begin - $display("*** TC%01d - Double block test started.", tc_ctr); + $display("*** TC%01d - Double block test started.", tc_ctr); // First block write_block(block0); @@ -525,7 +517,7 @@ module tb_sha1(); #(CLK_PERIOD); wait_ready(); read_digest(); - + if (digest_data == expected1) begin $display("TC%01d final block: OK.", tc_ctr); @@ -538,15 +530,18 @@ module tb_sha1(); error_ctr = error_ctr + 1; end - $display("*** TC%01d - Double block test done.", tc_ctr); + $display("*** TC%01d - Double block test done.", tc_ctr); tc_ctr = tc_ctr + 1; end endtask // double_block_test - + //---------------------------------------------------------------- // sha1_test - // The main test functionality. + // The main test functionality. + // + // Test cases taken from: + // http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf //---------------------------------------------------------------- initial begin : sha1_test @@ -563,7 +558,7 @@ module tb_sha1(); init_sim(); reset_dut(); check_name_version(); - + // TC1: Single block message: "abc". tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d; @@ -573,11 +568,11 @@ module tb_sha1(); // "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000; res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572; - + tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0; res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1; double_block_test(tc2_1, res2_1, tc2_2, res2_2); - + display_test_result(); $display("*** Simulation done. ***"); $finish; @@ -587,4 +582,3 @@ endmodule // tb_sha1 //====================================================================== // EOF tb_sha1.v //====================================================================== - diff --git a/src/tb/tb_sha1_core.v b/src/tb/tb_sha1_core.v index 2247c22..17416f3 100644 --- a/src/tb/tb_sha1_core.v +++ b/src/tb/tb_sha1_core.v @@ -8,7 +8,7 @@ // Author: Joachim Strombergson // Copyright (c) 2014, NORDUnet A/S // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -37,13 +37,8 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - module tb_sha1_core(); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -51,8 +46,8 @@ module tb_sha1_core(); parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = CLK_HALF_PERIOD * 2; - - + + //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- @@ -68,38 +63,38 @@ module tb_sha1_core(); wire tb_ready; wire [159 : 0] tb_digest; wire tb_digest_valid; - - - + + + //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- sha1_core dut( .clk(tb_clk), .reset_n(tb_reset_n), - + .init(tb_init), .next(tb_next), .block(tb_block), - + .ready(tb_ready), - + .digest(tb_digest), .digest_valid(tb_digest_valid) ); - + //---------------------------------------------------------------- // clk_gen // - // Clock generator process. + // Clock generator process. //---------------------------------------------------------------- - always + always begin : clk_gen #CLK_HALF_PERIOD tb_clk = !tb_clk; end // clk_gen - + //---------------------------------------------------------------- // sys_monitor @@ -113,59 +108,59 @@ module tb_sha1_core(); end end - + //---------------------------------------------------------------- // dump_dut_state() // // Dump the state of the dump when needed. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("State of DUT"); $display("------------"); $display("Inputs and outputs:"); - $display("init = 0x%01x, next = 0x%01x", + $display("init = 0x%01x, next = 0x%01x", dut.init, dut.next); $display("block = 0x%0128x", dut.block); - $display("ready = 0x%01x, valid = 0x%01x", + $display("ready = 0x%01x, valid = 0x%01x", dut.ready, dut.digest_valid); $display("digest = 0x%040x", dut.digest); - $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", + $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg); $display(""); - + $display("Control signals and counter:"); $display("sha1_ctrl_reg = 0x%01x", dut.sha1_ctrl_reg); - $display("digest_init = 0x%01x, digest_update = 0x%01x", + $display("digest_init = 0x%01x, digest_update = 0x%01x", dut.digest_init, dut.digest_update); - $display("state_init = 0x%01x, state_update = 0x%01x", + $display("state_init = 0x%01x, state_update = 0x%01x", dut.state_init, dut.state_update); - $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", + $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", dut.first_block, dut.ready_flag, dut.w_init); - $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", + $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg); $display(""); $display("State registers:"); - $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", + $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg, dut.e_reg); - $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", + $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new); $display(""); $display("State update values:"); - $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", + $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w); $display(""); end endtask // dump_dut_state - - + + //---------------------------------------------------------------- // reset_dut() //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -174,18 +169,18 @@ module tb_sha1_core(); end endtask // reset_dut - + //---------------------------------------------------------------- // init_sim() // // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin error_ctr = 0; tc_ctr = 0; - + tb_clk = 0; tb_reset_n = 1; @@ -195,13 +190,13 @@ module tb_sha1_core(); end endtask // init_dut - + //---------------------------------------------------------------- // display_test_result() // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_result(); + task display_test_result; begin if (error_ctr == 0) begin @@ -213,7 +208,7 @@ module tb_sha1_core(); end end endtask // display_test_result - + //---------------------------------------------------------------- // wait_ready() @@ -224,17 +219,17 @@ module tb_sha1_core(); // when the dut is actively processing and will in fact at some // point set the flag. //---------------------------------------------------------------- - task wait_ready(); + task wait_ready; begin while (!tb_ready) begin #(CLK_PERIOD); - + end end endtask // wait_ready - + //---------------------------------------------------------------- // single_block_test // @@ -253,25 +248,25 @@ module tb_sha1_core(); tb_init = 0; wait_ready(); - + if (tb_digest == expected) begin $display("*** TC %0d successful.", tc_number); $display(""); - end + end else begin $display("*** ERROR: TC %0d NOT successful.", tc_number); $display("Expected: 0x%040x", expected); $display("Got: 0x%040x", tb_digest); $display(""); - + error_ctr = error_ctr + 1; end end endtask // single_block_test - + //---------------------------------------------------------------- // double_block_test // @@ -298,7 +293,7 @@ module tb_sha1_core(); wait_ready(); db_digest1 = tb_digest; $display("*** TC %0d first block done.", tc_number); - + $display("*** TC %0d second block started.", tc_number); tb_block = block2; tb_next = 1; @@ -306,12 +301,12 @@ module tb_sha1_core(); tb_next = 0; wait_ready(); $display("*** TC %0d second block done.", tc_number); - + if (db_digest1 == expected1) begin $display("*** TC %0d first block successful", tc_number); $display(""); - end + end else begin $display("*** ERROR: TC %0d first block NOT successful", tc_number); @@ -320,12 +315,12 @@ module tb_sha1_core(); $display(""); db_error = 1; end - + if (db_digest1 == expected1) begin $display("*** TC %0d second block successful", tc_number); $display(""); - end + end else begin $display("*** ERROR: TC %0d second block NOT successful", tc_number); @@ -341,11 +336,14 @@ module tb_sha1_core(); end end endtask // double_block_test - - + + //---------------------------------------------------------------- // sha1_core_test - // The main test functionality. + // The main test functionality. + // + // Test cases taken from: + // http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf //---------------------------------------------------------------- initial begin : sha1_core_test @@ -356,14 +354,14 @@ module tb_sha1_core(); reg [159 : 0] res2_1; reg [511 : 0] tc2_2; reg [159 : 0] res2_2; - + $display(" -- Testbench for sha1 core started --"); init_sim(); dump_dut_state(); reset_dut(); dump_dut_state(); - + // TC1: Single block message: "abc". tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d; @@ -373,11 +371,11 @@ module tb_sha1_core(); // "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000; res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572; - + tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0; res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1; double_block_test(2, tc2_1, res2_1, tc2_2, res2_2); - + display_test_result(); $display("*** Simulation done."); $finish; diff --git a/src/tb/tb_sha1_w_mem.v b/src/tb/tb_sha1_w_mem.v index 337092d..1ee018f 100644 --- a/src/tb/tb_sha1_w_mem.v +++ b/src/tb/tb_sha1_w_mem.v @@ -37,11 +37,6 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - module tb_sha1_w_mem(); @@ -69,9 +64,9 @@ module tb_sha1_w_mem(); reg [511 : 0] tb_block; wire [31 : 0] tb_w; - reg [63 : 0] cycle_ctr; - reg [31 : 0] error_ctr; - reg [31 : 0] tc_ctr; + reg [63 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] tc_ctr; //---------------------------------------------------------------- @@ -128,7 +123,7 @@ module tb_sha1_w_mem(); // // Dump the current state of all W registers. //---------------------------------------------------------------- - task dump_w_state(); + task dump_w_state; begin $display("W state:"); @@ -158,7 +153,7 @@ module tb_sha1_w_mem(); //---------------------------------------------------------------- // reset_dut //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -171,7 +166,7 @@ module tb_sha1_w_mem(); //---------------------------------------------------------------- // init_sim //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin $display("*** Simulation init."); tb_clk = 0; @@ -190,7 +185,7 @@ module tb_sha1_w_mem(); // Dump the contents of the memory by directly reading from // the registers in the dut, not via the read port. //---------------------------------------------------------------- - task dump_mem(); + task dump_mem; begin $display("*** Dumping memory:"); $display("W[00] = 0x%08x", dut.w_mem[00]); @@ -220,7 +215,7 @@ module tb_sha1_w_mem(); // Test that W scheduling happens and work correctly. // Note: Currently not a self checking test case. //---------------------------------------------------------------- - task test_w_schedule(); + task test_w_schedule; begin $display("*** Test of W schedule processing. --"); tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; @@ -242,7 +237,7 @@ module tb_sha1_w_mem(); // Test that we can read data from all W registers. // Note: Currently not a self checking test case. //---------------------------------------------------------------- - task test_read_w(); + task test_read_w; reg [7 : 0] i; begin $display("*** Test of W read operations. --"); -- cgit v1.2.3