From 7527ad5bb6dc560a235398439863a6ee785ad2a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 8 Dec 2017 10:01:27 +0100 Subject: Syncecd SHA-1 core to github repo. No functional changes, but more compact code and a lot of minor fixes to silence warnings. --- src/rtl/sha1.v | 543 +++++++------------------------------------------ src/rtl/sha1_core.v | 74 +++---- src/rtl/sha1_w_mem.v | 73 +++---- src/tb/tb_sha1.v | 164 +++++++-------- src/tb/tb_sha1_core.v | 118 ++++++----- src/tb/tb_sha1_w_mem.v | 23 +-- 6 files changed, 276 insertions(+), 719 deletions(-) diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v index 835cadf..40d13bc 100644 --- a/src/rtl/sha1.v +++ b/src/rtl/sha1.v @@ -57,44 +57,27 @@ module sha1( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter ADDR_NAME0 = 8'h00; - parameter ADDR_NAME1 = 8'h01; - parameter ADDR_VERSION = 8'h02; - - parameter ADDR_CTRL = 8'h08; - parameter CTRL_INIT_BIT = 0; - parameter CTRL_NEXT_BIT = 1; - - parameter ADDR_STATUS = 8'h09; - parameter STATUS_READY_BIT = 0; - parameter STATUS_VALID_BIT = 1; - - parameter ADDR_BLOCK0 = 8'h10; - parameter ADDR_BLOCK1 = 8'h11; - parameter ADDR_BLOCK2 = 8'h12; - parameter ADDR_BLOCK3 = 8'h13; - parameter ADDR_BLOCK4 = 8'h14; - parameter ADDR_BLOCK5 = 8'h15; - parameter ADDR_BLOCK6 = 8'h16; - parameter ADDR_BLOCK7 = 8'h17; - parameter ADDR_BLOCK8 = 8'h18; - parameter ADDR_BLOCK9 = 8'h19; - parameter ADDR_BLOCK10 = 8'h1a; - parameter ADDR_BLOCK11 = 8'h1b; - parameter ADDR_BLOCK12 = 8'h1c; - parameter ADDR_BLOCK13 = 8'h1d; - parameter ADDR_BLOCK14 = 8'h1e; - parameter ADDR_BLOCK15 = 8'h1f; - - parameter ADDR_DIGEST0 = 8'h20; - parameter ADDR_DIGEST1 = 8'h21; - parameter ADDR_DIGEST2 = 8'h22; - parameter ADDR_DIGEST3 = 8'h23; - parameter ADDR_DIGEST4 = 8'h24; - - parameter CORE_NAME0 = 32'h73686131; // "sha1" - parameter CORE_NAME1 = 32'h20202020; // " " - parameter CORE_VERSION = 32'h302e3530; // "0.50" + localparam ADDR_NAME0 = 8'h00; + localparam ADDR_NAME1 = 8'h01; + localparam ADDR_VERSION = 8'h02; + + localparam ADDR_CTRL = 8'h08; + localparam CTRL_INIT_BIT = 0; + localparam CTRL_NEXT_BIT = 1; + + localparam ADDR_STATUS = 8'h09; + localparam STATUS_READY_BIT = 0; + localparam STATUS_VALID_BIT = 1; + + localparam ADDR_BLOCK0 = 8'h10; + localparam ADDR_BLOCK15 = 8'h1f; + + localparam ADDR_DIGEST0 = 8'h20; + localparam ADDR_DIGEST4 = 8'h24; + + localparam CORE_NAME0 = 32'h73686131; // "sha1" + localparam CORE_NAME1 = 32'h20202020; // " " + localparam CORE_VERSION = 32'h302e3630; // "0.60" //---------------------------------------------------------------- @@ -102,48 +85,14 @@ module sha1( //---------------------------------------------------------------- reg init_reg; reg init_new; - reg init_we; - reg init_set; reg next_reg; reg next_new; - reg next_we; - reg next_set; reg ready_reg; - reg [31 : 0] block0_reg; - reg block0_we; - reg [31 : 0] block1_reg; - reg block1_we; - reg [31 : 0] block2_reg; - reg block2_we; - reg [31 : 0] block3_reg; - reg block3_we; - reg [31 : 0] block4_reg; - reg block4_we; - reg [31 : 0] block5_reg; - reg block5_we; - reg [31 : 0] block6_reg; - reg block6_we; - reg [31 : 0] block7_reg; - reg block7_we; - reg [31 : 0] block8_reg; - reg block8_we; - reg [31 : 0] block9_reg; - reg block9_we; - reg [31 : 0] block10_reg; - reg block10_we; - reg [31 : 0] block11_reg; - reg block11_we; - reg [31 : 0] block12_reg; - reg block12_we; - reg [31 : 0] block13_reg; - reg block13_we; - reg [31 : 0] block14_reg; - reg block14_we; - reg [31 : 0] block15_reg; - reg block15_we; + reg [31 : 0] block_reg [0 : 15]; + reg block_we; reg [159 : 0] digest_reg; @@ -167,36 +116,32 @@ module sha1( //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign core_init = init_reg; - - assign core_next = next_reg; - - assign core_block = {block0_reg, block1_reg, block2_reg, block3_reg, - block4_reg, block5_reg, block6_reg, block7_reg, - block8_reg, block9_reg, block10_reg, block11_reg, - block12_reg, block13_reg, block14_reg, block15_reg}; + assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03], + block_reg[04], block_reg[05], block_reg[06], block_reg[07], + block_reg[08], block_reg[09], block_reg[10], block_reg[11], + block_reg[12], block_reg[13], block_reg[14], block_reg[15]}; assign read_data = tmp_read_data; - assign error = tmp_error; + assign error = tmp_error; //---------------------------------------------------------------- // core instantiation. //---------------------------------------------------------------- sha1_core core( - .clk(clk), - .reset_n(reset_n), + .clk(clk), + .reset_n(reset_n), - .init(core_init), - .next(core_next), + .init(init_reg), + .next(next_reg), - .block(core_block), + .block(core_block), - .ready(core_ready), + .ready(core_ready), - .digest(core_digest), - .digest_valid(core_digest_valid) - ); + .digest(core_digest), + .digest_valid(core_digest_valid) + ); //---------------------------------------------------------------- @@ -206,171 +151,35 @@ module sha1( // asynchronous active low reset. //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) - begin + begin : reg_update + integer i; + if (!reset_n) begin init_reg <= 0; next_reg <= 0; ready_reg <= 0; - digest_reg <= 160'h0000000000000000000000000000000000000000; + digest_reg <= 160'h0; digest_valid_reg <= 0; - block0_reg <= 32'h00000000; - block1_reg <= 32'h00000000; - block2_reg <= 32'h00000000; - block3_reg <= 32'h00000000; - block4_reg <= 32'h00000000; - block5_reg <= 32'h00000000; - block6_reg <= 32'h00000000; - block7_reg <= 32'h00000000; - block8_reg <= 32'h00000000; - block9_reg <= 32'h00000000; - block10_reg <= 32'h00000000; - block11_reg <= 32'h00000000; - block12_reg <= 32'h00000000; - block13_reg <= 32'h00000000; - block14_reg <= 32'h00000000; - block15_reg <= 32'h00000000; + + for (i = 0 ; i < 16 ; i = i + 1) + block_reg[i] <= 32'h0; end else begin ready_reg <= core_ready; digest_valid_reg <= core_digest_valid; + init_reg <= init_new; + next_reg <= next_new; - if (init_we) - begin - init_reg <= init_new; - end - - if (next_we) - begin - next_reg <= next_new; - end + if (block_we) + block_reg[address[3 : 0]] <= write_data; if (core_digest_valid) - begin - digest_reg <= core_digest; - end - - if (block0_we) - begin - block0_reg <= write_data; - end - - if (block1_we) - begin - block1_reg <= write_data; - end - - if (block2_we) - begin - block2_reg <= write_data; - end - - if (block3_we) - begin - block3_reg <= write_data; - end - - if (block4_we) - begin - block4_reg <= write_data; - end - - if (block5_we) - begin - block5_reg <= write_data; - end - - if (block6_we) - begin - block6_reg <= write_data; - end - - if (block7_we) - begin - block7_reg <= write_data; - end - - if (block8_we) - begin - block8_reg <= write_data; - end - - if (block9_we) - begin - block9_reg <= write_data; - end - - if (block10_we) - begin - block10_reg <= write_data; - end - - if (block11_we) - begin - block11_reg <= write_data; - end - - if (block12_we) - begin - block12_reg <= write_data; - end - - if (block13_we) - begin - block13_reg <= write_data; - end - - if (block14_we) - begin - block14_reg <= write_data; - end - - if (block15_we) - begin - block15_reg <= write_data; - end - + digest_reg <= core_digest; end end // reg_update - - //---------------------------------------------------------------- - // flag_reset - // - // Logic to reset init and next flags that has been set. - //---------------------------------------------------------------- - always @* - begin : flag_reset - init_new = 0; - init_we = 0; - next_new = 0; - next_we = 0; - - if (init_set) - begin - init_new = 1; - init_we = 1; - end - else if (init_reg) - begin - init_new = 0; - init_we = 1; - end - - if (next_set) - begin - next_new = 1; - next_we = 1; - end - else if (next_reg) - begin - next_new = 0; - next_we = 1; - end - end - - //---------------------------------------------------------------- // api // @@ -378,259 +187,49 @@ module sha1( //---------------------------------------------------------------- always @* begin : api - init_set = 0; - next_set = 0; - block0_we = 0; - block1_we = 0; - block2_we = 0; - block3_we = 0; - block4_we = 0; - block5_we = 0; - block6_we = 0; - block7_we = 0; - block8_we = 0; - block9_we = 0; - block10_we = 0; - block11_we = 0; - block12_we = 0; - block13_we = 0; - block14_we = 0; - block15_we = 0; - tmp_read_data = 32'h00000000; + init_new = 0; + next_new = 0; + block_we = 0; + tmp_read_data = 32'h0; tmp_error = 0; if (cs) begin if (we) begin - case (address) - // Write operations. - ADDR_CTRL: - begin - init_set = write_data[CTRL_INIT_BIT]; - next_set = write_data[CTRL_NEXT_BIT]; - end - - ADDR_BLOCK0: - begin - block0_we = 1; - end - - ADDR_BLOCK1: - begin - block1_we = 1; - end - - ADDR_BLOCK2: - begin - block2_we = 1; - end - - ADDR_BLOCK3: - begin - block3_we = 1; - end - - ADDR_BLOCK4: - begin - block4_we = 1; - end - - ADDR_BLOCK5: - begin - block5_we = 1; - end - - ADDR_BLOCK6: - begin - block6_we = 1; - end - - ADDR_BLOCK7: - begin - block7_we = 1; - end - - ADDR_BLOCK8: - begin - block8_we = 1; - end - - ADDR_BLOCK9: - begin - block9_we = 1; - end - - ADDR_BLOCK10: - begin - block10_we = 1; - end - - ADDR_BLOCK11: - begin - block11_we = 1; - end + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) + block_we = 1; - ADDR_BLOCK12: - begin - block12_we = 1; - end - - ADDR_BLOCK13: - begin - block13_we = 1; - end - - ADDR_BLOCK14: - begin - block14_we = 1; - end - - ADDR_BLOCK15: - begin - block15_we = 1; - end - - default: - begin - tmp_error = 1; - end - endcase // case (addr) + if (address == ADDR_CTRL) + begin + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + end end // if (write_read) - else begin + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) + tmp_read_data = block_reg[address[3 : 0]]; + + if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4)) + tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32]; + case (address) // Read operations. ADDR_NAME0: - begin - tmp_read_data = CORE_NAME0; - end + tmp_read_data = CORE_NAME0; ADDR_NAME1: - begin - tmp_read_data = CORE_NAME1; - end + tmp_read_data = CORE_NAME1; ADDR_VERSION: - begin - tmp_read_data = CORE_VERSION; - end + tmp_read_data = CORE_VERSION; ADDR_CTRL: - begin - tmp_read_data = {28'h0000000, 2'b00, next_reg, init_reg}; - end + tmp_read_data = {30'h0, next_reg, init_reg}; ADDR_STATUS: - begin - tmp_read_data = {28'h0000000, 2'b00, digest_valid_reg, ready_reg}; - end - - ADDR_BLOCK0: - begin - tmp_read_data = block0_reg; - end - - ADDR_BLOCK1: - begin - tmp_read_data = block1_reg; - end - - ADDR_BLOCK2: - begin - tmp_read_data = block2_reg; - end - - ADDR_BLOCK3: - begin - tmp_read_data = block3_reg; - end - - ADDR_BLOCK4: - begin - tmp_read_data = block4_reg; - end - - ADDR_BLOCK5: - begin - tmp_read_data = block5_reg; - end - - ADDR_BLOCK6: - begin - tmp_read_data = block6_reg; - end - - ADDR_BLOCK7: - begin - tmp_read_data = block7_reg; - end - - ADDR_BLOCK8: - begin - tmp_read_data = block8_reg; - end - - ADDR_BLOCK9: - begin - tmp_read_data = block9_reg; - end - - ADDR_BLOCK10: - begin - tmp_read_data = block10_reg; - end - - ADDR_BLOCK11: - begin - tmp_read_data = block11_reg; - end - - ADDR_BLOCK12: - begin - tmp_read_data = block12_reg; - end - - ADDR_BLOCK13: - begin - tmp_read_data = block13_reg; - end - - ADDR_BLOCK14: - begin - tmp_read_data = block14_reg; - end - - ADDR_BLOCK15: - begin - tmp_read_data = block15_reg; - end - - ADDR_DIGEST0: - begin - tmp_read_data = digest_reg[159 : 128]; - end - - ADDR_DIGEST1: - begin - tmp_read_data = digest_reg[127 : 96]; - end - - ADDR_DIGEST2: - begin - tmp_read_data = digest_reg[95 : 64]; - end - - ADDR_DIGEST3: - begin - tmp_read_data = digest_reg[63 : 32]; - end - - ADDR_DIGEST4: - begin - tmp_read_data = digest_reg[31 : 0]; - end + tmp_read_data = {30'h0, digest_valid_reg, ready_reg}; default: begin diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v index beb0cbd..e38da3b 100644 --- a/src/rtl/sha1_core.v +++ b/src/rtl/sha1_core.v @@ -67,8 +67,7 @@ module sha1_core( parameter CTRL_IDLE = 0; parameter CTRL_ROUNDS = 1; - parameter CTRL_DIGEST = 2; - parameter CTRL_DONE = 3; + parameter CTRL_DONE = 2; //---------------------------------------------------------------- @@ -161,18 +160,18 @@ module sha1_core( begin : reg_update if (!reset_n) begin - a_reg <= 32'h00000000; - b_reg <= 32'h00000000; - c_reg <= 32'h00000000; - d_reg <= 32'h00000000; - e_reg <= 32'h00000000; - H0_reg <= 32'h00000000; - H1_reg <= 32'h00000000; - H2_reg <= 32'h00000000; - H3_reg <= 32'h00000000; - H4_reg <= 32'h00000000; + a_reg <= 32'h0; + b_reg <= 32'h0; + c_reg <= 32'h0; + d_reg <= 32'h0; + e_reg <= 32'h0; + H0_reg <= 32'h0; + H1_reg <= 32'h0; + H2_reg <= 32'h0; + H3_reg <= 32'h0; + H4_reg <= 32'h0; digest_valid_reg <= 0; - round_ctr_reg <= 7'b0000000; + round_ctr_reg <= 7'b0; sha1_ctrl_reg <= CTRL_IDLE; end else @@ -196,19 +195,13 @@ module sha1_core( end if (round_ctr_we) - begin - round_ctr_reg <= round_ctr_new; - end + round_ctr_reg <= round_ctr_new; if (digest_valid_we) - begin - digest_valid_reg <= digest_valid_new; - end + digest_valid_reg <= digest_valid_new; if (sha1_ctrl_we) - begin - sha1_ctrl_reg <= sha1_ctrl_new; - end + sha1_ctrl_reg <= sha1_ctrl_new; end end // reg_update @@ -220,11 +213,11 @@ module sha1_core( //---------------------------------------------------------------- always @* begin : digest_logic - H0_new = 32'h00000000; - H1_new = 32'h00000000; - H2_new = 32'h00000000; - H3_new = 32'h00000000; - H4_new = 32'h00000000; + H0_new = 32'h0; + H1_new = 32'h0; + H2_new = 32'h0; + H3_new = 32'h0; + H4_new = 32'h0; H_we = 0; if (digest_init) @@ -262,15 +255,15 @@ module sha1_core( reg [31 : 0] k; reg [31 : 0] t; - a5 = 32'h00000000; - f = 32'h00000000; - k = 32'h00000000; - t = 32'h00000000; - a_new = 32'h00000000; - b_new = 32'h00000000; - c_new = 32'h00000000; - d_new = 32'h00000000; - e_new = 32'h00000000; + a5 = 32'h0; + f = 32'h0; + k = 32'h0; + t = 32'h0; + a_new = 32'h0; + b_new = 32'h0; + c_new = 32'h0; + d_new = 32'h0; + e_new = 32'h0; a_e_we = 0; if (state_init) @@ -416,20 +409,15 @@ module sha1_core( if (round_ctr_reg == SHA1_ROUNDS) begin - sha1_ctrl_new = CTRL_DIGEST; + sha1_ctrl_new = CTRL_DONE; sha1_ctrl_we = 1; end end - CTRL_DIGEST: - begin - digest_update = 1; - sha1_ctrl_new = CTRL_DONE; - sha1_ctrl_we = 1; - end CTRL_DONE: begin + digest_update = 1; digest_valid_new = 1; digest_valid_we = 1; sha1_ctrl_new = CTRL_IDLE; diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v index 4bc307d..f50741e 100644 --- a/src/rtl/sha1_w_mem.v +++ b/src/rtl/sha1_w_mem.v @@ -116,25 +116,13 @@ module sha1_w_mem( //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin : reg_update + integer i; + if (!reset_n) begin - w_mem[00] <= 32'h00000000; - w_mem[01] <= 32'h00000000; - w_mem[02] <= 32'h00000000; - w_mem[03] <= 32'h00000000; - w_mem[04] <= 32'h00000000; - w_mem[05] <= 32'h00000000; - w_mem[06] <= 32'h00000000; - w_mem[07] <= 32'h00000000; - w_mem[08] <= 32'h00000000; - w_mem[09] <= 32'h00000000; - w_mem[10] <= 32'h00000000; - w_mem[11] <= 32'h00000000; - w_mem[12] <= 32'h00000000; - w_mem[13] <= 32'h00000000; - w_mem[14] <= 32'h00000000; - w_mem[15] <= 32'h00000000; - w_ctr_reg <= 7'h00; + for (i = 0 ; i < 16 ; i = i + 1) + w_mem[i] <= 32'h0; + sha1_w_mem_ctrl_reg <= CTRL_IDLE; end else @@ -160,15 +148,10 @@ module sha1_w_mem( end if (w_ctr_we) - begin - w_ctr_reg <= w_ctr_new; - end + w_ctr_reg <= w_ctr_new; if (sha1_w_mem_ctrl_we) - begin - sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new; - end - + sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new; end end // reg_update @@ -180,7 +163,7 @@ module sha1_w_mem( // memory or the next w value calculated. //---------------------------------------------------------------- always @* - begin : w_schedule + begin : select_w if (w_ctr_reg < 16) begin w_tmp = w_mem[w_ctr_reg[3 : 0]]; @@ -189,7 +172,7 @@ module sha1_w_mem( begin w_tmp = w_new; end - end // w_schedule + end // select_w //---------------------------------------------------------------- @@ -206,22 +189,22 @@ module sha1_w_mem( reg [31 : 0] w_13; reg [31 : 0] w_16; - w_mem00_new = 32'h00000000; - w_mem01_new = 32'h00000000; - w_mem02_new = 32'h00000000; - w_mem03_new = 32'h00000000; - w_mem04_new = 32'h00000000; - w_mem05_new = 32'h00000000; - w_mem06_new = 32'h00000000; - w_mem07_new = 32'h00000000; - w_mem08_new = 32'h00000000; - w_mem09_new = 32'h00000000; - w_mem10_new = 32'h00000000; - w_mem11_new = 32'h00000000; - w_mem12_new = 32'h00000000; - w_mem13_new = 32'h00000000; - w_mem14_new = 32'h00000000; - w_mem15_new = 32'h00000000; + w_mem00_new = 32'h0; + w_mem01_new = 32'h0; + w_mem02_new = 32'h0; + w_mem03_new = 32'h0; + w_mem04_new = 32'h0; + w_mem05_new = 32'h0; + w_mem06_new = 32'h0; + w_mem07_new = 32'h0; + w_mem08_new = 32'h0; + w_mem09_new = 32'h0; + w_mem10_new = 32'h0; + w_mem11_new = 32'h0; + w_mem12_new = 32'h0; + w_mem13_new = 32'h0; + w_mem14_new = 32'h0; + w_mem15_new = 32'h0; w_mem_we = 0; w_0 = w_mem[0]; @@ -283,12 +266,12 @@ module sha1_w_mem( //---------------------------------------------------------------- always @* begin : w_ctr - w_ctr_new = 7'h00; + w_ctr_new = 7'h0; w_ctr_we = 0; if (w_ctr_rst) begin - w_ctr_new = 7'h00; + w_ctr_new = 7'h0; w_ctr_we = 1; end @@ -337,7 +320,7 @@ module sha1_w_mem( end end endcase // case (sha1_ctrl_reg) - end // sha1_ctrl_fsm + end // sha1_w_mem_fsm endmodule // sha1_w_mem //====================================================================== diff --git a/src/tb/tb_sha1.v b/src/tb/tb_sha1.v index 9c339a0..f454034 100644 --- a/src/tb/tb_sha1.v +++ b/src/tb/tb_sha1.v @@ -8,7 +8,7 @@ // Author: Joachim Strombergson // Copyright (c) 2014, NORDUnet A/S // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -37,13 +37,8 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - module tb_sha1(); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -52,7 +47,7 @@ module tb_sha1(); parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = CLK_HALF_PERIOD * 2; - + parameter ADDR_NAME0 = 8'h00; parameter ADDR_NAME1 = 8'h01; parameter ADDR_VERSION = 8'h02; @@ -66,7 +61,7 @@ module tb_sha1(); parameter ADDR_STATUS = 8'h09; parameter STATUS_READY_BIT = 0; parameter STATUS_VALID_BIT = 1; - + parameter ADDR_BLOCK0 = 8'h10; parameter ADDR_BLOCK1 = 8'h11; parameter ADDR_BLOCK2 = 8'h12; @@ -83,14 +78,14 @@ module tb_sha1(); parameter ADDR_BLOCK13 = 8'h1d; parameter ADDR_BLOCK14 = 8'h1e; parameter ADDR_BLOCK15 = 8'h1f; - + parameter ADDR_DIGEST0 = 8'h20; parameter ADDR_DIGEST1 = 8'h21; parameter ADDR_DIGEST2 = 8'h22; parameter ADDR_DIGEST3 = 8'h23; parameter ADDR_DIGEST4 = 8'h24; - + //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- @@ -108,35 +103,35 @@ module tb_sha1(); reg [31 : 0] read_data; reg [159 : 0] digest_data; - - + + //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- sha1 dut( .clk(tb_clk), .reset_n(tb_reset_n), - + .cs(tb_cs), .we(tb_write_read), - + .address(tb_address), .write_data(tb_data_in), .read_data(tb_data_out), - .error(tb_error) + .error(tb_error) ); - + //---------------------------------------------------------------- // clk_gen // - // Clock generator process. + // Clock generator process. //---------------------------------------------------------------- - always + always begin : clk_gen #CLK_HALF_PERIOD tb_clk = !tb_clk; end // clk_gen - + //---------------------------------------------------------------- // sys_monitor @@ -147,7 +142,7 @@ module tb_sha1(); begin dump_core_state(); end - + if (DEBUG_TOP) begin dump_top_state(); @@ -157,13 +152,13 @@ module tb_sha1(); cycle_ctr = cycle_ctr + 1; end - + //---------------------------------------------------------------- // dump_top_state() // // Dump state of the the top of the dut. //---------------------------------------------------------------- - task dump_top_state(); + task dump_top_state; begin $display("State of top"); $display("-------------"); @@ -172,24 +167,21 @@ module tb_sha1(); $display("address = 0x%02x, write_data = 0x%08x", dut.address, dut.write_data); $display("error = 0x%01x, read_data = 0x%08x", dut.error, dut.read_data); $display(""); - + $display("Control and status flags:"); - $display("init = 0x%01x, next = 0x%01x, ready = 0x%01x", + $display("init = 0x%01x, next = 0x%01x, ready = 0x%01x", dut.init_reg, dut.next_reg, dut.ready_reg); $display(""); $display("block registers:"); - $display("block0_reg = 0x%08x, block1_reg = 0x%08x, block2_reg = 0x%08x, block3_reg = 0x%08x", - dut.block0_reg, dut.block1_reg, dut.block2_reg, dut.block3_reg); - - $display("block4_reg = 0x%08x, block5_reg = 0x%08x, block6_reg = 0x%08x, block7_reg = 0x%08x", - dut.block4_reg, dut.block5_reg, dut.block6_reg, dut.block7_reg); - - $display("block8_reg = 0x%08x, block9_reg = 0x%08x, block10_reg = 0x%08x, block11_reg = 0x%08x", - dut.block8_reg, dut.block9_reg, dut.block10_reg, dut.block11_reg); - - $display("block12_reg = 0x%08x, block13_reg = 0x%08x, block14_reg = 0x%08x, block15_reg = 0x%08x", - dut.block12_reg, dut.block13_reg, dut.block14_reg, dut.block15_reg); + $display("block0 = 0x%08x, block1 = 0x%08x, block2 = 0x%08x, block3 = 0x%08x", + dut.block_reg[00], dut.block_reg[01], dut.block_reg[02], dut.block_reg[03]); + $display("block4 = 0x%08x, block5 = 0x%08x, block6 = 0x%08x, block7 = 0x%08x", + dut.block_reg[04], dut.block_reg[05], dut.block_reg[06], dut.block_reg[07]); + $display("block8 = 0x%08x, block9 = 0x%08x, block10 = 0x%08x, block11 = 0x%08x", + dut.block_reg[08], dut.block_reg[09], dut.block_reg[10], dut.block_reg[11]); + $display("block12 = 0x%08x, block13 = 0x%08x, block14 = 0x%08x, block15 = 0x%08x", + dut.block_reg[12], dut.block_reg[13], dut.block_reg[14], dut.block_reg[15]); $display(""); $display("Digest registers:"); @@ -198,59 +190,59 @@ module tb_sha1(); end endtask // dump_top_state - + //---------------------------------------------------------------- // dump_core_state() // // Dump the state of the core inside the dut. //---------------------------------------------------------------- - task dump_core_state(); + task dump_core_state; begin $display("State of core"); $display("-------------"); $display("Inputs and outputs:"); - $display("init = 0x%01x, next = 0x%01x", + $display("init = 0x%01x, next = 0x%01x", dut.core.init, dut.core.next); $display("block = 0x%0128x", dut.core.block); - $display("ready = 0x%01x, valid = 0x%01x", + $display("ready = 0x%01x, valid = 0x%01x", dut.core.ready, dut.core.digest_valid); $display("digest = 0x%040x", dut.core.digest); - $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", + $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", dut.core.H0_reg, dut.core.H1_reg, dut.core.H2_reg, dut.core.H3_reg, dut.core.H4_reg); $display(""); - + $display("Control signals and counter:"); $display("sha1_ctrl_reg = 0x%01x", dut.core.sha1_ctrl_reg); - $display("digest_init = 0x%01x, digest_update = 0x%01x", + $display("digest_init = 0x%01x, digest_update = 0x%01x", dut.core.digest_init, dut.core.digest_update); - $display("state_init = 0x%01x, state_update = 0x%01x", + $display("state_init = 0x%01x, state_update = 0x%01x", dut.core.state_init, dut.core.state_update); - $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", + $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", dut.core.first_block, dut.core.ready_flag, dut.core.w_init); - $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", + $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", dut.core.round_ctr_inc, dut.core.round_ctr_rst, dut.core.round_ctr_reg); $display(""); $display("State registers:"); - $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", + $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", dut.core.a_reg, dut.core.b_reg, dut.core.c_reg, dut.core.d_reg, dut.core.e_reg); - $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", + $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", dut.core.a_new, dut.core.b_new, dut.core.c_new, dut.core.d_new, dut.core.e_new); $display(""); $display("State update values:"); - $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", + $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", dut.core.state_logic.f, dut.core.state_logic.k, dut.core.state_logic.t, dut.core.w); $display(""); end endtask // dump_core_state - - + + //---------------------------------------------------------------- // reset_dut() //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -259,19 +251,19 @@ module tb_sha1(); end endtask // reset_dut - + //---------------------------------------------------------------- // init_sim() // // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 32'h00000000; error_ctr = 32'h00000000; tc_ctr = 32'h00000000; - + tb_clk = 0; tb_reset_n = 0; tb_cs = 0; @@ -281,13 +273,13 @@ module tb_sha1(); end endtask // init_dut - + //---------------------------------------------------------------- // display_test_result() // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_result(); + task display_test_result; begin if (error_ctr == 0) begin @@ -300,8 +292,8 @@ module tb_sha1(); end end endtask // display_test_result - - + + //---------------------------------------------------------------- // wait_ready() // @@ -312,17 +304,17 @@ module tb_sha1(); // when the dut is actively processing and will in fact at some // point set the flag. //---------------------------------------------------------------- - task wait_ready(); + task wait_ready; begin read_data = 0; - + while (read_data == 0) begin read_word(ADDR_STATUS); end end endtask // wait_ready - + //---------------------------------------------------------------- // read_word() @@ -347,7 +339,7 @@ module tb_sha1(); end end endtask // read_word - + //---------------------------------------------------------------- // write_word() @@ -362,7 +354,7 @@ module tb_sha1(); $display("*** Writing 0x%08x to 0x%02x.", word, address); $display(""); end - + tb_address = address; tb_data_in = word; tb_cs = 1; @@ -373,7 +365,7 @@ module tb_sha1(); end endtask // write_word - + //---------------------------------------------------------------- // write_block() // @@ -400,13 +392,13 @@ module tb_sha1(); end endtask // write_block - + //---------------------------------------------------------------- // check_name_version() // // Read the name and version from the DUT. //---------------------------------------------------------------- - task check_name_version(); + task check_name_version; reg [31 : 0] name0; reg [31 : 0] name1; reg [31 : 0] version; @@ -426,7 +418,7 @@ module tb_sha1(); version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]); end endtask // check_name_version - + //---------------------------------------------------------------- // read_digest() @@ -434,7 +426,7 @@ module tb_sha1(); // Read the digest in the dut. The resulting digest will be // available in the global variable digest_data. //---------------------------------------------------------------- - task read_digest(); + task read_digest; begin read_word(ADDR_DIGEST0); digest_data[159 : 128] = read_data; @@ -448,8 +440,8 @@ module tb_sha1(); digest_data[31 : 0] = read_data; end endtask // read_digest - - + + //---------------------------------------------------------------- // single_block_test() // @@ -460,8 +452,8 @@ module tb_sha1(); input [159 : 0] expected ); begin - $display("*** TC%01d - Single block test started.", tc_ctr); - + $display("*** TC%01d - Single block test started.", tc_ctr); + write_block(block); write_word(ADDR_CTRL, CTRL_INIT_VALUE); #(CLK_PERIOD); @@ -479,12 +471,12 @@ module tb_sha1(); $display("TC%01d: Got: 0x%040x", tc_ctr, digest_data); error_ctr = error_ctr + 1; end - $display("*** TC%01d - Single block test done.", tc_ctr); + $display("*** TC%01d - Single block test done.", tc_ctr); tc_ctr = tc_ctr + 1; end endtask // single_block_test - - + + //---------------------------------------------------------------- // double_block_test() // @@ -498,7 +490,7 @@ module tb_sha1(); input [159 : 0] expected1 ); begin - $display("*** TC%01d - Double block test started.", tc_ctr); + $display("*** TC%01d - Double block test started.", tc_ctr); // First block write_block(block0); @@ -525,7 +517,7 @@ module tb_sha1(); #(CLK_PERIOD); wait_ready(); read_digest(); - + if (digest_data == expected1) begin $display("TC%01d final block: OK.", tc_ctr); @@ -538,15 +530,18 @@ module tb_sha1(); error_ctr = error_ctr + 1; end - $display("*** TC%01d - Double block test done.", tc_ctr); + $display("*** TC%01d - Double block test done.", tc_ctr); tc_ctr = tc_ctr + 1; end endtask // double_block_test - + //---------------------------------------------------------------- // sha1_test - // The main test functionality. + // The main test functionality. + // + // Test cases taken from: + // http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf //---------------------------------------------------------------- initial begin : sha1_test @@ -563,7 +558,7 @@ module tb_sha1(); init_sim(); reset_dut(); check_name_version(); - + // TC1: Single block message: "abc". tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d; @@ -573,11 +568,11 @@ module tb_sha1(); // "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000; res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572; - + tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0; res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1; double_block_test(tc2_1, res2_1, tc2_2, res2_2); - + display_test_result(); $display("*** Simulation done. ***"); $finish; @@ -587,4 +582,3 @@ endmodule // tb_sha1 //====================================================================== // EOF tb_sha1.v //====================================================================== - diff --git a/src/tb/tb_sha1_core.v b/src/tb/tb_sha1_core.v index 2247c22..17416f3 100644 --- a/src/tb/tb_sha1_core.v +++ b/src/tb/tb_sha1_core.v @@ -8,7 +8,7 @@ // Author: Joachim Strombergson // Copyright (c) 2014, NORDUnet A/S // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -37,13 +37,8 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - module tb_sha1_core(); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -51,8 +46,8 @@ module tb_sha1_core(); parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = CLK_HALF_PERIOD * 2; - - + + //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- @@ -68,38 +63,38 @@ module tb_sha1_core(); wire tb_ready; wire [159 : 0] tb_digest; wire tb_digest_valid; - - - + + + //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- sha1_core dut( .clk(tb_clk), .reset_n(tb_reset_n), - + .init(tb_init), .next(tb_next), .block(tb_block), - + .ready(tb_ready), - + .digest(tb_digest), .digest_valid(tb_digest_valid) ); - + //---------------------------------------------------------------- // clk_gen // - // Clock generator process. + // Clock generator process. //---------------------------------------------------------------- - always + always begin : clk_gen #CLK_HALF_PERIOD tb_clk = !tb_clk; end // clk_gen - + //---------------------------------------------------------------- // sys_monitor @@ -113,59 +108,59 @@ module tb_sha1_core(); end end - + //---------------------------------------------------------------- // dump_dut_state() // // Dump the state of the dump when needed. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("State of DUT"); $display("------------"); $display("Inputs and outputs:"); - $display("init = 0x%01x, next = 0x%01x", + $display("init = 0x%01x, next = 0x%01x", dut.init, dut.next); $display("block = 0x%0128x", dut.block); - $display("ready = 0x%01x, valid = 0x%01x", + $display("ready = 0x%01x, valid = 0x%01x", dut.ready, dut.digest_valid); $display("digest = 0x%040x", dut.digest); - $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", + $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x", dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg); $display(""); - + $display("Control signals and counter:"); $display("sha1_ctrl_reg = 0x%01x", dut.sha1_ctrl_reg); - $display("digest_init = 0x%01x, digest_update = 0x%01x", + $display("digest_init = 0x%01x, digest_update = 0x%01x", dut.digest_init, dut.digest_update); - $display("state_init = 0x%01x, state_update = 0x%01x", + $display("state_init = 0x%01x, state_update = 0x%01x", dut.state_init, dut.state_update); - $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", + $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", dut.first_block, dut.ready_flag, dut.w_init); - $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", + $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg); $display(""); $display("State registers:"); - $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", + $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x", dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg, dut.e_reg); - $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", + $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x", dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new); $display(""); $display("State update values:"); - $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", + $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,", dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w); $display(""); end endtask // dump_dut_state - - + + //---------------------------------------------------------------- // reset_dut() //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -174,18 +169,18 @@ module tb_sha1_core(); end endtask // reset_dut - + //---------------------------------------------------------------- // init_sim() // // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin error_ctr = 0; tc_ctr = 0; - + tb_clk = 0; tb_reset_n = 1; @@ -195,13 +190,13 @@ module tb_sha1_core(); end endtask // init_dut - + //---------------------------------------------------------------- // display_test_result() // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_result(); + task display_test_result; begin if (error_ctr == 0) begin @@ -213,7 +208,7 @@ module tb_sha1_core(); end end endtask // display_test_result - + //---------------------------------------------------------------- // wait_ready() @@ -224,17 +219,17 @@ module tb_sha1_core(); // when the dut is actively processing and will in fact at some // point set the flag. //---------------------------------------------------------------- - task wait_ready(); + task wait_ready; begin while (!tb_ready) begin #(CLK_PERIOD); - + end end endtask // wait_ready - + //---------------------------------------------------------------- // single_block_test // @@ -253,25 +248,25 @@ module tb_sha1_core(); tb_init = 0; wait_ready(); - + if (tb_digest == expected) begin $display("*** TC %0d successful.", tc_number); $display(""); - end + end else begin $display("*** ERROR: TC %0d NOT successful.", tc_number); $display("Expected: 0x%040x", expected); $display("Got: 0x%040x", tb_digest); $display(""); - + error_ctr = error_ctr + 1; end end endtask // single_block_test - + //---------------------------------------------------------------- // double_block_test // @@ -298,7 +293,7 @@ module tb_sha1_core(); wait_ready(); db_digest1 = tb_digest; $display("*** TC %0d first block done.", tc_number); - + $display("*** TC %0d second block started.", tc_number); tb_block = block2; tb_next = 1; @@ -306,12 +301,12 @@ module tb_sha1_core(); tb_next = 0; wait_ready(); $display("*** TC %0d second block done.", tc_number); - + if (db_digest1 == expected1) begin $display("*** TC %0d first block successful", tc_number); $display(""); - end + end else begin $display("*** ERROR: TC %0d first block NOT successful", tc_number); @@ -320,12 +315,12 @@ module tb_sha1_core(); $display(""); db_error = 1; end - + if (db_digest1 == expected1) begin $display("*** TC %0d second block successful", tc_number); $display(""); - end + end else begin $display("*** ERROR: TC %0d second block NOT successful", tc_number); @@ -341,11 +336,14 @@ module tb_sha1_core(); end end endtask // double_block_test - - + + //---------------------------------------------------------------- // sha1_core_test - // The main test functionality. + // The main test functionality. + // + // Test cases taken from: + // http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf //---------------------------------------------------------------- initial begin : sha1_core_test @@ -356,14 +354,14 @@ module tb_sha1_core(); reg [159 : 0] res2_1; reg [511 : 0] tc2_2; reg [159 : 0] res2_2; - + $display(" -- Testbench for sha1 core started --"); init_sim(); dump_dut_state(); reset_dut(); dump_dut_state(); - + // TC1: Single block message: "abc". tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d; @@ -373,11 +371,11 @@ module tb_sha1_core(); // "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000; res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572; - + tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0; res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1; double_block_test(2, tc2_1, res2_1, tc2_2, res2_2); - + display_test_result(); $display("*** Simulation done."); $finish; diff --git a/src/tb/tb_sha1_w_mem.v b/src/tb/tb_sha1_w_mem.v index 337092d..1ee018f 100644 --- a/src/tb/tb_sha1_w_mem.v +++ b/src/tb/tb_sha1_w_mem.v @@ -37,11 +37,6 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - module tb_sha1_w_mem(); @@ -69,9 +64,9 @@ module tb_sha1_w_mem(); reg [511 : 0] tb_block; wire [31 : 0] tb_w; - reg [63 : 0] cycle_ctr; - reg [31 : 0] error_ctr; - reg [31 : 0] tc_ctr; + reg [63 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] tc_ctr; //---------------------------------------------------------------- @@ -128,7 +123,7 @@ module tb_sha1_w_mem(); // // Dump the current state of all W registers. //---------------------------------------------------------------- - task dump_w_state(); + task dump_w_state; begin $display("W state:"); @@ -158,7 +153,7 @@ module tb_sha1_w_mem(); //---------------------------------------------------------------- // reset_dut //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -171,7 +166,7 @@ module tb_sha1_w_mem(); //---------------------------------------------------------------- // init_sim //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin $display("*** Simulation init."); tb_clk = 0; @@ -190,7 +185,7 @@ module tb_sha1_w_mem(); // Dump the contents of the memory by directly reading from // the registers in the dut, not via the read port. //---------------------------------------------------------------- - task dump_mem(); + task dump_mem; begin $display("*** Dumping memory:"); $display("W[00] = 0x%08x", dut.w_mem[00]); @@ -220,7 +215,7 @@ module tb_sha1_w_mem(); // Test that W scheduling happens and work correctly. // Note: Currently not a self checking test case. //---------------------------------------------------------------- - task test_w_schedule(); + task test_w_schedule; begin $display("*** Test of W schedule processing. --"); tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; @@ -242,7 +237,7 @@ module tb_sha1_w_mem(); // Test that we can read data from all W registers. // Note: Currently not a self checking test case. //---------------------------------------------------------------- - task test_read_w(); + task test_read_w; reg [7 : 0] i; begin $display("*** Test of W read operations. --"); -- cgit v1.2.3