| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2014-03-17 | Removed redundant flag reset wires. | Joachim Strömbergson | |
| 2014-03-16 | Added wait to allow the ready flag to be dropped with resettable flags. ↵ | Joachim Strömbergson | |
| Fixed name of clock delay parameter. | |||
| 2014-03-14 | Updating interface. Addding self resetting control regs. Fixing missing ↵ | Joachim Strömbergson | |
| input port declaration that caused errors during simulation in ModelSim. | |||
| 2014-02-23 | Updated W memory module with new sliding window version. Updated README with ↵ | Joachim Strömbergson | |
| more info. | |||
| 2014-02-21 | Adding all testbenches. | Joachim Strömbergson | |
| 2014-02-21 | Adding all rtl source files for the sha-1 core. | Joachim Strömbergson | |
| 2014-02-21 | Adding functional model in Python. Used to drive RTL development. | Joachim Strömbergson | |
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index : core/hash/sha1 | |
| Verilog implementation of the SHA-1 cryptographic hash function | git repositories |
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