core/hash/sha1 - Verilog implementation of the SHA-1 cryptographic hash function

Age	Commit message (Collapse)	Author
2018-10-03	Restricted write access for control bits to when the core is ready.	Joachim Strömbergson

2018-04-27	Removed obsolete defines.	Joachim Strömbergson

2018-04-27	Removed redundant FSM from the W memory.	Joachim Strömbergson

2017-12-15	Removing stale wires.	Joachim Strömbergson

2017-12-08	Syncecd SHA-1 core to github repo. No functional changes, but more compact ↵	Joachim Strömbergson
	code and a lot of minor fixes to silence warnings.
2015-12-13	whack copyrights	Paul Selkirk

2015-03-31	Revert streamlined wrapper, and don't delay register reads.	Paul Selkirk

2015-03-17	Rearrange cores.	Paul Selkirk

2014-12-05	There is an END to this, according to Paul.	Joachim Strömbergson

2014-12-05	Adding a separate digiest update state.	Joachim Strömbergson

2014-11-07	Changed to asynch reset.	Joachim Strömbergson

2014-11-06	(1) Minor fixes of nits found by the verilator linter. (2) Removed trailing ↵	Joachim Strömbergson
	whitespace.
2014-04-01	Update of the Python model to support NIST dual block message test as well ↵	Joachim Strömbergson
	as a test case with a huge message.
2014-03-17	Removed redundant flag reset wires.	Joachim Strömbergson

2014-03-16	Added wait to allow the ready flag to be dropped with resettable flags. ↵	Joachim Strömbergson
	Fixed name of clock delay parameter.
2014-03-14	Updating interface. Addding self resetting control regs. Fixing missing ↵	Joachim Strömbergson
	input port declaration that caused errors during simulation in ModelSim.
2014-02-23	Updated W memory module with new sliding window version. Updated README with ↵	Joachim Strömbergson
	more info.
2014-02-21	Adding all testbenches.	Joachim Strömbergson

2014-02-21	Adding all rtl source files for the sha-1 core.	Joachim Strömbergson

2014-02-21	Adding functional model in Python. Used to drive RTL development.	Joachim Strömbergson