| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-12-15 | Removing stale wires. | Joachim Strömbergson | |
| 2017-12-08 | Syncecd SHA-1 core to github repo. No functional changes, but more compact ↵ | Joachim Strömbergson | |
| code and a lot of minor fixes to silence warnings. | |||
| 2015-12-13 | whack copyrights | Paul Selkirk | |
| 2015-03-31 | Revert streamlined wrapper, and don't delay register reads. | Paul Selkirk | |
| 2015-03-17 | Rearrange cores. | Paul Selkirk | |
| 2014-11-07 | Changed to asynch reset. | Joachim Strömbergson | |
| 2014-03-17 | Removed redundant flag reset wires. | Joachim Strömbergson | |
| 2014-03-14 | Updating interface. Addding self resetting control regs. Fixing missing ↵ | Joachim Strömbergson | |
| input port declaration that caused errors during simulation in ModelSim. | |||
| 2014-02-21 | Adding all rtl source files for the sha-1 core. | Joachim Strömbergson | |
 |
index : core/hash/sha1 | |
| Verilog implementation of the SHA-1 cryptographic hash function | git repositories |
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