diff options
Diffstat (limited to 'src/rtl/sha1_w_mem.v')
| -rw-r--r-- | src/rtl/sha1_w_mem.v | 73 |
1 files changed, 28 insertions, 45 deletions
diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v index 4bc307d..f50741e 100644 --- a/src/rtl/sha1_w_mem.v +++ b/src/rtl/sha1_w_mem.v @@ -116,25 +116,13 @@ module sha1_w_mem( //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin : reg_update + integer i; + if (!reset_n) begin - w_mem[00] <= 32'h00000000; - w_mem[01] <= 32'h00000000; - w_mem[02] <= 32'h00000000; - w_mem[03] <= 32'h00000000; - w_mem[04] <= 32'h00000000; - w_mem[05] <= 32'h00000000; - w_mem[06] <= 32'h00000000; - w_mem[07] <= 32'h00000000; - w_mem[08] <= 32'h00000000; - w_mem[09] <= 32'h00000000; - w_mem[10] <= 32'h00000000; - w_mem[11] <= 32'h00000000; - w_mem[12] <= 32'h00000000; - w_mem[13] <= 32'h00000000; - w_mem[14] <= 32'h00000000; - w_mem[15] <= 32'h00000000; - w_ctr_reg <= 7'h00; + for (i = 0 ; i < 16 ; i = i + 1) + w_mem[i] <= 32'h0; + sha1_w_mem_ctrl_reg <= CTRL_IDLE; end else @@ -160,15 +148,10 @@ module sha1_w_mem( end if (w_ctr_we) - begin - w_ctr_reg <= w_ctr_new; - end + w_ctr_reg <= w_ctr_new; if (sha1_w_mem_ctrl_we) - begin - sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new; - end - + sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new; end end // reg_update @@ -180,7 +163,7 @@ module sha1_w_mem( // memory or the next w value calculated. //---------------------------------------------------------------- always @* - begin : w_schedule + begin : select_w if (w_ctr_reg < 16) begin w_tmp = w_mem[w_ctr_reg[3 : 0]]; @@ -189,7 +172,7 @@ module sha1_w_mem( begin w_tmp = w_new; end - end // w_schedule + end // select_w //---------------------------------------------------------------- @@ -206,22 +189,22 @@ module sha1_w_mem( reg [31 : 0] w_13; reg [31 : 0] w_16; - w_mem00_new = 32'h00000000; - w_mem01_new = 32'h00000000; - w_mem02_new = 32'h00000000; - w_mem03_new = 32'h00000000; - w_mem04_new = 32'h00000000; - w_mem05_new = 32'h00000000; - w_mem06_new = 32'h00000000; - w_mem07_new = 32'h00000000; - w_mem08_new = 32'h00000000; - w_mem09_new = 32'h00000000; - w_mem10_new = 32'h00000000; - w_mem11_new = 32'h00000000; - w_mem12_new = 32'h00000000; - w_mem13_new = 32'h00000000; - w_mem14_new = 32'h00000000; - w_mem15_new = 32'h00000000; + w_mem00_new = 32'h0; + w_mem01_new = 32'h0; + w_mem02_new = 32'h0; + w_mem03_new = 32'h0; + w_mem04_new = 32'h0; + w_mem05_new = 32'h0; + w_mem06_new = 32'h0; + w_mem07_new = 32'h0; + w_mem08_new = 32'h0; + w_mem09_new = 32'h0; + w_mem10_new = 32'h0; + w_mem11_new = 32'h0; + w_mem12_new = 32'h0; + w_mem13_new = 32'h0; + w_mem14_new = 32'h0; + w_mem15_new = 32'h0; w_mem_we = 0; w_0 = w_mem[0]; @@ -283,12 +266,12 @@ module sha1_w_mem( //---------------------------------------------------------------- always @* begin : w_ctr - w_ctr_new = 7'h00; + w_ctr_new = 7'h0; w_ctr_we = 0; if (w_ctr_rst) begin - w_ctr_new = 7'h00; + w_ctr_new = 7'h0; w_ctr_we = 1; end @@ -337,7 +320,7 @@ module sha1_w_mem( end end endcase // case (sha1_ctrl_reg) - end // sha1_ctrl_fsm + end // sha1_w_mem_fsm endmodule // sha1_w_mem //====================================================================== |