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+++ b/README.md
@@ -11,21 +11,43 @@ https://github.com/secworks/sha1
 
 ## Implementation details ##
 
-### Altera Cyclone IV GX ###
-Implementation using Altera Quartus-II 13.1 with a EP4CGX22CF19C6 device
-as target.
-* 10718 LEs
-* 3575 Regs
-* 103 MHz
+### Altera Cyclone FPGAs ###
+Implementation results using Altera Quartus-II 13.1.
+
+***Altera Cyclone IV E***
+- EP4CE6F17C6
+- 2913 LEs
+- 1527 regs
+- 107 MHz
+
+***Altera Cyclone IV GX***
+- EP4CGX22CF19C6
+- 2814 LEs
+- 1527 regs
+- 105 MHz
+
+***Altera Cyclone V***
+- 5CGXFC7C7F23C8
+- 1124 ALMs
+- 1527 regs
+- 104 MHz
 
 
 ## TODO ##
 * Extensive functional verification in real HW.
 * Add Wishbone interface.
+* Add results for Xilinx and possibly some other FPGA device.
 * Documentation
 
 
 ## Status ##
+***(2014-02-23):***
+
+New version of the W memory module that quite drastically improves
+resource utilization. And a bit better performance too. Also added some
+new results for other Altera devices.
+
+
 ***(2014-02-21):***
 
 Moved the core to Cryptech.