From 5d15271e9fafb42575caa0dccffa48e68277ee89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Mon, 17 Mar 2014 09:55:01 +0100 Subject: Changing from blocking to correct, non-blocking assignments in reg update. --- src/rtl/uart_core.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/rtl/uart_core.v b/src/rtl/uart_core.v index 5596958..af2f5a0 100644 --- a/src/rtl/uart_core.v +++ b/src/rtl/uart_core.v @@ -216,7 +216,7 @@ module uart_core( if (rxd_syn_we) begin - rxd_syn_reg = rxd_syn_new; + rxd_syn_reg <= rxd_syn_new; end if (erx_ctrl_we) @@ -226,12 +226,12 @@ module uart_core( if (txd_we) begin - txd_reg = txd_new; + txd_reg <= txd_new; end if (txd_byte_we) begin - txd_byte_reg = txd_byte_new; + txd_byte_reg <= txd_byte_new; end if (txd_bit_ctr_we) @@ -246,7 +246,7 @@ module uart_core( if (txd_ack_we) begin - txd_ack_reg = txd_ack_new; + txd_ack_reg <= txd_ack_new; end if (etx_ctrl_we) -- cgit v1.2.3