index
:
core/comm/uart
master
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog
git repositories
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
toolruns
/
Makefile
Age
Commit message (
Collapse
)
Author
2014-03-13
Adding makefile to build and run uart simulations.
Joachim StroĢmbergson