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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2014-03-17 09:13:00 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2014-03-17 09:13:00 +0100 |
| commit | b250c13a0dda87d74ef35e8d1fb4f04e0b30949c (patch) | |
| tree | 1bb2c4acee24a05d34cfd77dc6c4e3f423e268db /src/rtl | |
| parent | 6169f43f900da676a3c177029b5a8a4e1baa2a7a (diff) | |
Adding size constraints to constant definitions to remove synthesis warnings.
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/uart.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/rtl/uart.v b/src/rtl/uart.v index abf3934..d5a5a86 100644 --- a/src/rtl/uart.v +++ b/src/rtl/uart.v @@ -99,11 +99,11 @@ module uart( // Clock: 50 MHz // Bitrate: 19200 bps // Divisor = 50*10E6 / 9600 = 5208 - parameter DEFAULT_CLK_RATE = 5208; + parameter DEFAULT_CLK_RATE = 16'd5208; parameter DEFAULT_HALF_CLK_RATE = DEFAULT_CLK_RATE / 2; - parameter DEFAULT_DATA_BITS = 8; - parameter DEFAULT_STOP_BITS = 1; + parameter DEFAULT_DATA_BITS = 4'h8; + parameter DEFAULT_STOP_BITS = 2'h2; //---------------------------------------------------------------- |