From 94433d14317b57558e6ccebe10148cdb9976f723 Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Wed, 29 Apr 2015 13:21:52 -0400
Subject: Cleanup: add error port, remove dummy register.

---
 src/rtl/i2c_regs.v | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/src/rtl/i2c_regs.v b/src/rtl/i2c_regs.v
index ec1c186..66b5830 100644
--- a/src/rtl/i2c_regs.v
+++ b/src/rtl/i2c_regs.v
@@ -37,15 +37,19 @@
 
 module comm_regs
   (
+   // Clock and reset.
    input wire           clk,
    input wire           rst,
 
+   // Control.
    input wire           cs,
    input wire           we,
 
+   // Data ports.
    input wire [ 7 : 0]  address,
    input wire [31 : 0]  write_data,
-   output wire [31 : 0] read_data
+   output wire [31 : 0] read_data,
+   output wire          error
    );
 
 
@@ -56,7 +60,6 @@ module comm_regs
    localparam ADDR_CORE_NAME0   = 8'h00;
    localparam ADDR_CORE_NAME1   = 8'h01;
    localparam ADDR_CORE_VERSION = 8'h02;
-   localparam ADDR_DUMMY_REG    = 8'hFF;    // general-purpose register
 
    // Core ID constants.
    localparam CORE_NAME0   = 32'h69326320;  // "i2c "
@@ -68,39 +71,39 @@ module comm_regs
    // Wires.
    //----------------------------------------------------------------
    reg [31: 0]          tmp_read_data;
-
-   // dummy register to check that you can actually write something
-   reg [31: 0]          reg_dummy;
+   reg                  write_error;
+   reg                  read_error;
 
 
    //----------------------------------------------------------------
    // Concurrent connectivity for ports etc.
    //----------------------------------------------------------------
    assign read_data = tmp_read_data;
-   
+   assign error     = write_error | read_error;
+
 
    //----------------------------------------------------------------
    // storage registers for mapping memory to core interface
    //----------------------------------------------------------------
-   always @ (posedge clk or posedge rst)
+   always @ (posedge clk)
      begin
-        if (rst)
-          begin
-             reg_dummy <= {32{1'b0}};
-          end
-        else if (cs && we)
+        write_error <= 0;
+
+        if (cs && we)
           begin
              // write operations
              case (address)
-               ADDR_DUMMY_REG:
-                 reg_dummy <= write_data;
-             endcase
+               // no writeable registers
+               default:
+                 write_error <= 1;
+               endcase
           end
      end
 
    always @*
      begin
         tmp_read_data = 32'h00000000;
+        read_error    = 0;
 
         if (cs && !we)
           begin
@@ -112,8 +115,8 @@ module comm_regs
                  tmp_read_data = CORE_NAME1;
                ADDR_CORE_VERSION:
                  tmp_read_data = CORE_VERSION;
-               ADDR_DUMMY_REG:
-                 tmp_read_data = reg_dummy;
+               default:
+                 read_error = 1;
              endcase
           end
      end
-- 
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