i2c_device_addr as output

2 files changed, 10 insertions, 8 deletions

diff --git a/src/rtl/i2c.v b/src/rtl/i2c.v
index 112ad70..4a3bc5d 100644
--- a/src/rtl/i2c.v
+++ b/src/rtl/i2c.v
@@ -45,7 +45,7 @@ module i2c(
 	    input wire 		 SCL,
 	    input wire 		 SDA,
 	    output wire 	 SDA_pd,
-	    input wire [7:0] 	 i2c_device_addr,
+	    output wire [6:0] 	 i2c_device_addr,
 
             // Internal receive interface.
             output wire 	 rxd_syn,
@@ -92,7 +92,6 @@ module i2c(
   wire 	        core_SCL;
   wire 	        core_SDA;
   wire 		core_SDA_pd;
-  wire [7:0] 	core_i2c_device_addr;
 
   wire          core_rxd_syn;
   wire [7 : 0]  core_rxd_data;
@@ -112,7 +111,6 @@ module i2c(
   assign core_SCL      = SCL;
   assign core_SDA      = SDA;
   assign SDA_pd        = core_SDA_pd;
-  assign core_i2c_device_addr = i2c_device_addr;
 
   assign rxd_syn       = core_rxd_syn;
   assign rxd_data      = core_rxd_data;
@@ -141,7 +139,7 @@ module i2c(
 		.SCL(core_SCL),
 		.SDA(core_SDA),
 		.SDA_pd(core_SDA_pd),
-		.i2c_device_addr(core_i2c_device_addr),
+		.i2c_device_addr(i2c_device_addr),
 
                  // Internal receive interface.
                  .rxd_syn(core_rxd_syn),
diff --git a/src/rtl/i2c_core.v b/src/rtl/i2c_core.v
index f5d7c87..89bcba7 100644
--- a/src/rtl/i2c_core.v
+++ b/src/rtl/i2c_core.v
@@ -37,6 +37,12 @@
 ///////////
 `timescale 1 ns / 1 ps
 
+// This file is based on https://github.com/bunnie/novena-gpbb-fpga/blob/master/novena-gpbb.srcs/sources_1/imports/imports/i2c_slave.v
+//
+// For Cryptech, we replaced the register interface with the rxd/txd
+// interface to coretest, and changed i2c_device_addr from an 8-bit
+// input to a 7-bit output.
+
 module i2c_core (
                  input wire 	    clk,
                  input wire 	    reset,
@@ -45,7 +51,7 @@ module i2c_core (
 		 input wire 	    SCL,
 		 input wire 	    SDA,
 		 output reg 	    SDA_pd,
-		 input wire [7:0]   i2c_device_addr,
+		 output wire [6:0]  i2c_device_addr,
 
                  // Internal receive interface.
                  output wire 	    rxd_syn,
@@ -139,7 +145,7 @@ module i2c_core (
    assign rxd_data = I2C_wdata;
    assign rxd_syn  = rxd_syn_reg;
    assign txd_ack  = txd_ack_reg;
-
+   assign i2c_device_addr = I2C_daddr[7:1];
 
    ////////// code begins here
    always @ (posedge clk) begin
@@ -164,9 +170,7 @@ module i2c_core (
 	end
 	I2C_ACK_DADDR: begin // depending upon W/R bit state, go to one of two branches
 	   I2C_nstate = (SCL_cstate == SCL_FALL) ?
-			(I2C_daddr[7:1] == i2c_device_addr[7:1]) ?
 			(I2C_daddr[0] == 1'b0 ? I2C_WR_DATA : I2C_TXD_SYN) :
-			I2C_WAITSTOP : // !I2C_daddr match
 			I2C_ACK_DADDR; // !SCL_FALL
 	end