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-rw-r--r--src/rtl/eim_regs.v75
1 files changed, 37 insertions, 38 deletions
diff --git a/src/rtl/eim_regs.v b/src/rtl/eim_regs.v
index 09a51dc..5903ee6 100644
--- a/src/rtl/eim_regs.v
+++ b/src/rtl/eim_regs.v
@@ -70,9 +70,9 @@ module comm_regs
reg [31: 0] tmp_read_data;
// dummy register to check that you can actually write something
- reg [31: 0] reg_dummy;
+ reg [31: 0] reg_dummy;
+
-
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
@@ -80,43 +80,42 @@ module comm_regs
//----------------------------------------------------------------
- // Access Handler
+ // storage registers for mapping memory to core interface
//----------------------------------------------------------------
- always @(posedge clk)
- //
- if (rst)
- reg_dummy <= {32{1'b0}};
- else if (cs) begin
- //
- if (we) begin
- //
- // WRITE handler
- //
- case (address)
- ADDR_DUMMY_REG:
- reg_dummy <= write_data;
- endcase
- //
- end else begin
- //
- // READ handler
- //
- case (address)
- ADDR_CORE_NAME0:
- tmp_read_data <= CORE_NAME0;
- ADDR_CORE_NAME1:
- tmp_read_data <= CORE_NAME1;
- ADDR_CORE_VERSION:
- tmp_read_data <= CORE_VERSION;
- ADDR_DUMMY_REG:
- tmp_read_data <= reg_dummy;
- //
- default:
- tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
- endcase
- //
- end
- //
+ always @ (posedge clk or posedge rst)
+ begin
+ if (rst)
+ begin
+ reg_dummy <= {32{1'b0}};
+ end
+ else if (cs && we)
+ begin
+ // write operations
+ case (address)
+ ADDR_DUMMY_REG:
+ reg_dummy <= write_data;
+ endcase
+ end
+ end
+
+ always @*
+ begin
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ case (address)
+ ADDR_CORE_NAME0:
+ tmp_read_data = CORE_NAME0;
+ ADDR_CORE_NAME1:
+ tmp_read_data = CORE_NAME1;
+ ADDR_CORE_VERSION:
+ tmp_read_data = CORE_VERSION;
+ ADDR_DUMMY_REG:
+ tmp_read_data = reg_dummy;
+ endcase
+ end
end
endmodule