Change reset to active-low.

3 files changed, 5 insertions, 7 deletions

diff --git a/src/rtl/eim.v b/src/rtl/eim.v
index dcbd226..2a07a14 100644
--- a/src/rtl/eim.v
+++ b/src/rtl/eim.v
@@ -14,7 +14,7 @@ module eim
 
    // system clock and reset
    input wire 	       sys_clk,
-   input wire 	       sys_rst,
+   input wire 	       sys_rst_n,
 
    // EIM interface to cores
    output wire [16: 0] sys_eim_addr,
@@ -27,8 +27,6 @@ module eim
    output wire 	       led_pin		// LED on edge close to the FPGA.
    );
 
-   // XXX add NAME0/NAME1/VERSION
-
    //----------------------------------------------------------------
    // EIM Arbiter
    //
@@ -66,7 +64,7 @@ module eim
    eim_indicator led
      (
       .sys_clk(sys_clk),
-      .sys_rst(sys_rst),
+      .sys_rst_n(sys_rst_n),
       .eim_active(sys_eim_wr | sys_eim_rd),
       .led_out(led_pin)
       );
diff --git a/src/rtl/eim_indicator.v b/src/rtl/eim_indicator.v
index cf9751d..b665ea5 100644
--- a/src/rtl/eim_indicator.v
+++ b/src/rtl/eim_indicator.v
@@ -39,7 +39,7 @@
 module eim_indicator
   (
    input wire  sys_clk,
-   input wire  sys_rst,
+   input wire  sys_rst_n,
    input wire  eim_active,
    output wire led_out
    );
@@ -56,7 +56,7 @@ module eim_indicator
 
    always @(posedge sys_clk)
      //
-     if (sys_rst)                       cnt <= {CNT_BITS{1'b0}};
+     if (!sys_rst_n)                    cnt <= {CNT_BITS{1'b0}};
      else if (cnt > {CNT_BITS{1'b0}})   cnt <= cnt - 1'b1;
      else if (eim_active)               cnt <= {CNT_BITS{1'b1}};
 
diff --git a/src/rtl/eim_regs.v b/src/rtl/eim_regs.v
index 6372045..2f4c3df 100644
--- a/src/rtl/eim_regs.v
+++ b/src/rtl/eim_regs.v
@@ -39,7 +39,7 @@ module comm_regs
   (
    // Clock and reset.
    input wire           clk,
-   input wire           rst,
+   input wire           reset_n,
 
    // Control.
    input wire           cs,