From 1721ef5b165aee52554675f6ceb1e3a1fc2fb031 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 23 Aug 2018 09:53:03 +0200 Subject: (1) Updated qr interface to include clock and reset needed for internal pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support. --- toolruns/Makefile | 54 ++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 16 deletions(-) (limited to 'toolruns') diff --git a/toolruns/Makefile b/toolruns/Makefile index 6f94769..d8e6ad3 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -36,49 +36,71 @@ # #=================================================================== -CORE_SRC=../src/rtl/chacha_core.v ../src/rtl/chacha_qr.v -CORE_TB_SRC=../src/tb/tb_chacha_core.v +QR_SRC = ../src/rtl/chacha_qr.v +QR_TB_SRC = ../src/tb/tb_chacha_qr.v -TOP_SRC=../src/rtl/chacha.v $(CORE_SRC) -TOP_TB_SRC=../src/tb/tb_chacha.v +CORE_SRC = ../src/rtl/chacha_core.v $(QR_SRC) +CORE_TB_SRC = ../src/tb/tb_chacha_core.v -CC=iverilog +TOP_SRC = ../src/rtl/chacha.v $(CORE_SRC) +TOP_TB_SRC = ../src/tb/tb_chacha.v +CC = iverilog +CC_FLAGS = -Wall -all: top core +LINT = verilator +LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME + + +all: top core qr top: $(TOP_TB_SRC) $(TOP_SRC) - $(CC) -o top.sim $(TOP_TB_SRC) $(TOP_SRC) + $(CC) $(CC_FLAGS) -o top.sim $(TOP_TB_SRC) $(TOP_SRC) core: $(CORE_TB_SRC) $(CORE_SRC) - $(CC) -o core.sim $(CORE_SRC) $(CORE_TB_SRC) + $(CC) $(CC_FLAGS) -o core.sim $(CORE_SRC) $(CORE_TB_SRC) -sim-core: core.sim - ./core.sim +qr: $(QR_TB_SRC) $(QR_SRC) + $(CC) $(CC_FLAGS) -o qr.sim $(QR_SRC) $(QR_TB_SRC) -sim-top: top.sim +sim-top: top ./top.sim +sim-core: core + ./core.sim + + +sim-qr: qr + ./qr.sim + + +lint: $(TOP_SRC) + $(LINT) $(LINT_FLAGS) $(TOP_SRC) + + help: @echo "Supported targets:" @echo "------------------" @echo "all: Build all simulation targets." @echo "top: Build the top simulation target." - @echo "core: Build the top simulation target." - @echo "sim-top: Run top level simulation." - @echo "sim-core: Run core level simulation." + @echo "core: Build the core simulation target." + @echo "qr : Build the qr simulation target." + @echo "sim-top: Run top simulation." + @echo "sim-core: Run core simulation." + @echo "sim-qr: Run qr simulation." + @echo "lint: Lint the design." @echo "debug: Print the internal varibles." clean: - rm -f core.sim rm -f top.sim + rm -f core.sim + rm -f qr.sim #=================================================================== # EOF Makefile #=================================================================== - -- cgit v1.2.3