From 6bac922a4d138363c483b55fd2027f0c660fd5e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 16 Oct 2018 10:14:05 +0200 Subject: Adding width specification, fixed order and other nits as part of ceckning that all registers are properly reset. --- src/rtl/chacha.v | 6 +++--- src/rtl/chacha_core.v | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/rtl/chacha.v b/src/rtl/chacha.v index bc891f7..8bfaba6 100644 --- a/src/rtl/chacha.v +++ b/src/rtl/chacha.v @@ -173,9 +173,9 @@ module chacha( integer i; if (!reset_n) begin - init_reg <= 0; - next_reg <= 0; - keylen_reg <= 0; + init_reg <= 1'h0; + next_reg <= 1'h0; + keylen_reg <= 1'h0; rounds_reg <= 5'h0; iv_reg[0] <= 32'h0; iv_reg[1] <= 32'h0; diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v index 6cb1e51..cc91327 100644 --- a/src/rtl/chacha_core.v +++ b/src/rtl/chacha_core.v @@ -279,13 +279,13 @@ module chacha_core( state_reg[i] <= 32'h0; data_out_reg <= 512'h0; - data_out_valid_reg <= 0; + data_out_valid_reg <= 1'h0; qr_ctr_reg <= QR0; - dr_ctr_reg <= 0; + dr_ctr_reg <= 4'h0; block0_ctr_reg <= 32'h0; block1_ctr_reg <= 32'h0; + ready_reg <= 1'h1; chacha_ctrl_reg <= CTRL_IDLE; - ready_reg <= 1; end else begin -- cgit v1.2.3