From 1721ef5b165aee52554675f6ceb1e3a1fc2fb031 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Thu, 23 Aug 2018 09:53:03 +0200
Subject: (1) Updated qr interface to include clock and reset needed for
 internal pipeline registers. (2) Added testbench for the qr module. (3) Added
 qr simulation target. (4) Added lint support.

---
 src/rtl/chacha_core.v | 12 ++++++++++++
 src/rtl/chacha_qr.v   | 29 +++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

(limited to 'src/rtl')

diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v
index 5f496a4..d68f783 100644
--- a/src/rtl/chacha_core.v
+++ b/src/rtl/chacha_core.v
@@ -191,6 +191,9 @@ module chacha_core(
   // Instantiation of the qr modules.
   //----------------------------------------------------------------
   chacha_qr qr0(
+                .clk(clk),
+                .reset_n(reset_n),
+
                 .a(qr0_a),
                 .b(qr0_b),
                 .c(qr0_c),
@@ -203,6 +206,9 @@ module chacha_core(
                );
 
   chacha_qr qr1(
+                .clk(clk),
+                .reset_n(reset_n),
+
                 .a(qr1_a),
                 .b(qr1_b),
                 .c(qr1_c),
@@ -215,6 +221,9 @@ module chacha_core(
                );
 
   chacha_qr qr2(
+                .clk(clk),
+                .reset_n(reset_n),
+
                 .a(qr2_a),
                 .b(qr2_b),
                 .c(qr2_c),
@@ -227,6 +236,9 @@ module chacha_core(
                );
 
   chacha_qr qr3(
+                .clk(clk),
+                .reset_n(reset_n),
+
                 .a(qr3_a),
                 .b(qr3_b),
                 .c(qr3_c),
diff --git a/src/rtl/chacha_qr.v b/src/rtl/chacha_qr.v
index 42e644c..e1ddbd8 100644
--- a/src/rtl/chacha_qr.v
+++ b/src/rtl/chacha_qr.v
@@ -40,6 +40,9 @@
 //======================================================================
 
 module chacha_qr(
+                 input wire           clk,
+                 input wire           reset_n,
+
                  input wire [31 : 0]  a,
                  input wire [31 : 0]  b,
                  input wire [31 : 0]  c,
@@ -51,6 +54,13 @@ module chacha_qr(
                  output wire [31 : 0] d_prim
                 );
 
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg [31 : 0] a0_reg;
+  reg [31 : 0] a0_new;
+
+
   //----------------------------------------------------------------
   // Wires.
   //----------------------------------------------------------------
@@ -69,6 +79,23 @@ module chacha_qr(
   assign d_prim = internal_d_prim;
 
 
+  //----------------------------------------------------------------
+  // reg_update
+  //----------------------------------------------------------------
+  always @ (posedge clk)
+    begin : reg_update
+      if (!reset_n)
+        begin
+          a0_reg <= 32'h0;
+        end
+
+      else
+        begin
+          a0_reg <= a0_new;
+        end
+    end // reg_update
+
+
   //----------------------------------------------------------------
   // qr
   //
@@ -93,6 +120,8 @@ module chacha_qr(
       reg [31 : 0] d3;
 
       a0 = a + b;
+      a0_new = a + b;
+
       d0 = d ^ a0;
       d1 = {d0[15 : 0], d0[31 : 16]};
       c0 = c + d1;
-- 
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