From 158aa5ae7b98eb458d99116ff639b6afaf158efb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 23 Aug 2018 10:59:40 +0200 Subject: (1) Adding pipeline register update code and a set of pipeline registers. Registers are not connected at the this stage. (2) Added self testing tetst cases and debug outputs to observe internal behaviour. --- src/rtl/chacha_qr.v | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'src/rtl') diff --git a/src/rtl/chacha_qr.v b/src/rtl/chacha_qr.v index e1ddbd8..5189030 100644 --- a/src/rtl/chacha_qr.v +++ b/src/rtl/chacha_qr.v @@ -59,6 +59,10 @@ module chacha_qr( //---------------------------------------------------------------- reg [31 : 0] a0_reg; reg [31 : 0] a0_new; +// reg [31 : 0] a1_reg; +// reg [31 : 0] a1_new; +// reg [31 : 0] c0_reg; +// reg [31 : 0] c0_new; //---------------------------------------------------------------- @@ -87,11 +91,15 @@ module chacha_qr( if (!reset_n) begin a0_reg <= 32'h0; +// a1_reg <= 32'h0; +// c0_reg <= 32'h0; end else begin a0_reg <= a0_new; +// a1_reg <= a1_new; +// c0_reg <= c0_new; end end // reg_update @@ -120,14 +128,20 @@ module chacha_qr( reg [31 : 0] d3; a0 = a + b; - a0_new = a + b; + a0_new = a0; d0 = d ^ a0; d1 = {d0[15 : 0], d0[31 : 16]}; + c0 = c + d1; +// c0_new = c0; + b0 = b ^ c0; b1 = {b0[19 : 0], b0[31 : 20]}; + a1 = a0 + b1; +// a1_new = a1; + d2 = d1 ^ a1; d3 = {d2[23 : 0], d2[31 : 24]}; c1 = c0 + d3; -- cgit v1.2.3