From 58f30c1e67b57e26ade0234107fbfb6f17b8af66 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Thu, 30 Aug 2018 08:49:22 +0200
Subject: Adding two more pipeline registers in the qr module. Added two more
 wait cycles.

---
 src/rtl/chacha_qr.v | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'src/rtl/chacha_qr.v')

diff --git a/src/rtl/chacha_qr.v b/src/rtl/chacha_qr.v
index ba68d51..ec29c70 100644
--- a/src/rtl/chacha_qr.v
+++ b/src/rtl/chacha_qr.v
@@ -59,10 +59,10 @@ module chacha_qr(
   //----------------------------------------------------------------
   reg [31 : 0] a0_reg;
   reg [31 : 0] a0_new;
-//  reg [31 : 0] a1_reg;
-//  reg [31 : 0] a1_new;
-//  reg [31 : 0] c0_reg;
-//  reg [31 : 0] c0_new;
+  reg [31 : 0] a1_reg;
+  reg [31 : 0] a1_new;
+  reg [31 : 0] c0_reg;
+  reg [31 : 0] c0_new;
 
 
   //----------------------------------------------------------------
@@ -91,15 +91,15 @@ module chacha_qr(
       if (!reset_n)
         begin
           a0_reg <= 32'h0;
-//          a1_reg <= 32'h0;
-//          c0_reg <= 32'h0;
+          a1_reg <= 32'h0;
+          c0_reg <= 32'h0;
         end
 
       else
         begin
           a0_reg <= a0_new;
-//          a1_reg <= a1_new;
-//          c0_reg <= c0_new;
+          a1_reg <= a1_new;
+          c0_reg <= c0_new;
         end
     end // reg_update
 
@@ -134,21 +134,21 @@ module chacha_qr(
       d1 = {d0[15 : 0], d0[31 : 16]};
 
       c0 = c + d1;
-//      c0_new = c0;
+      c0_new = c0;
 
-      b0 = b ^ c0;
+      b0 = b ^ c0_reg;
       b1 = {b0[19 : 0], b0[31 : 20]};
 
       a1 = a0_reg + b1;
-//      a1_new = a1;
+      a1_new = a1;
 
-      d2 = d1 ^ a1;
+      d2 = d1 ^ a1_reg;
       d3 = {d2[23 : 0], d2[31 : 24]};
-      c1 = c0 + d3;
+      c1 = c0_reg + d3;
       b2 = b1 ^ c1;
       b3 = {b2[24 : 0], b2[31 : 25]};
 
-      internal_a_prim = a1;
+      internal_a_prim = a1_reg;
       internal_b_prim = b3;
       internal_c_prim = c1;
       internal_d_prim = d3;
-- 
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