| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-08-23 | Debugged pipeline register and state update. All test cases ok.timing_fix | Joachim Strömbergson | |
| 2018-08-23 | Added missing define. | Joachim Strömbergson | |
| 2016-12-28 | (1) Cleanup of top an core code with no functional changes. The code is now ↵cleanup | Joachim Strömbergson | |
| much more compact. (2) Fixed how the QR modules are used in parallel to actually work in parallel. This increases performance. (3) Changed registers into arrays and cleaned up how operands and data are accessed. This decreased total design size. | |||
| 2014-09-03 | Adding testbenches for core and top. | Joachim Strömbergson | |
 |
index : core/cipher/chacha | |
| Verilog 2001 implementation of the ChaCha stream cipher | git repositories |
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