Hardening the API to block writes to contol signals when core is performing operations. Also blocking access to data out when core is busy. Minor cleanup of defines. Changed init and next flags to automatically toggle back to zero.

1 files changed, 32 insertions, 25 deletions

diff --git a/src/rtl/chacha.v b/src/rtl/chacha.v
index 8bfaba6..360ff1a 100644
--- a/src/rtl/chacha.v
+++ b/src/rtl/chacha.v
@@ -91,8 +91,10 @@ module chacha(
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
   reg          init_reg;
+  reg          init_new;
+
   reg          next_reg;
-  reg          ctrl_we;
+  reg          next_new;
 
   reg          keylen_reg;
   reg          keylen_we;
@@ -188,11 +190,8 @@ module chacha(
         end
       else
         begin
-          if (ctrl_we)
-            begin
-              init_reg <= write_data[CTRL_INIT_BIT];
-              next_reg <= write_data[CTRL_NEXT_BIT];
-            end
+          init_reg <= init_new;
+          next_reg <= next_new;
 
           if (keylen_we)
             keylen_reg <= write_data[KEYLEN_BIT];
@@ -217,35 +216,42 @@ module chacha(
   //----------------------------------------------------------------
   always @*
     begin : addr_decoder
-      ctrl_we       = 0;
-      keylen_we     = 0;
-      rounds_we     = 0;
-      key_we        = 0;
-      iv_we         = 0;
-      data_in_we    = 0;
+      init_new      = 1'h0;
+      next_new      = 1'h0;
+      keylen_we     = 1'h0;
+      rounds_we     = 1'h0;
+      key_we        = 1'h0;
+      iv_we         = 1'h0;
+      data_in_we    = 1'h0;
       tmp_read_data = 32'h0;
 
       if (cs)
         begin
           if (we)
             begin
-              if (address == ADDR_CTRL)
-                ctrl_we = 1;
+              if (core_ready)
+                begin
+                  if (address == ADDR_CTRL)
+                    begin
+                      init_new <= write_data[CTRL_INIT_BIT];
+                      next_new <= write_data[CTRL_NEXT_BIT];
+                    end
 
-              if (address == ADDR_KEYLEN)
-                keylen_we = 1;
+                  if (address == ADDR_KEYLEN)
+                    keylen_we = 1;
 
-              if (address == ADDR_ROUNDS)
-                rounds_we = 1;
+                  if (address == ADDR_ROUNDS)
+                    rounds_we = 1;
 
-              if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
-                key_we = 1;
+                  if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+                    key_we = 1;
 
-              if ((address >= ADDR_IV0) && (address <= ADDR_IV1))
-                iv_we = 1;
+                  if ((address >= ADDR_IV0) && (address <= ADDR_IV1))
+                    iv_we = 1;
 
-              if ((address >= ADDR_DATA_IN0) && (address <= ADDR_DATA_IN15))
-                data_in_we = 1;
+                  if ((address >= ADDR_DATA_IN0) && (address <= ADDR_DATA_IN15))
+                    data_in_we = 1;
+                end
             end // if (we)
 
           else
@@ -254,7 +260,8 @@ module chacha(
                 tmp_read_data = key_reg[address[2 : 0]];
 
               if ((address >= ADDR_DATA_OUT0) && (address <= ADDR_DATA_OUT15))
-                tmp_read_data = core_data_out[(15 - (address - ADDR_DATA_OUT0)) * 32 +: 32];
+                if (core_ready)
+                  tmp_read_data = core_data_out[(15 - (address - ADDR_DATA_OUT0)) * 32 +: 32];
 
               case (address)
                 ADDR_NAME0:   tmp_read_data = CORE_NAME0;