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-rw-r--r--src/rtl/aes_encipher_block.v18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v
index 094653a..29a555e 100644
--- a/src/rtl/aes_encipher_block.v
+++ b/src/rtl/aes_encipher_block.v
@@ -196,6 +196,15 @@ module aes_encipher_block(
reg [2 : 0] update_type;
reg [31 : 0] muxed_sboxw;
+ reg [31 : 0] sboxw0;
+ reg [31 : 0] sboxw1;
+ reg [31 : 0] sboxw2;
+ reg [31 : 0] sboxw3;
+ wire [31 : 0] new_sboxw0;
+ wire [31 : 0] new_sboxw1;
+ wire [31 : 0] new_sboxw2;
+ wire [31 : 0] new_sboxw3;
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
@@ -207,6 +216,15 @@ module aes_encipher_block(
//----------------------------------------------------------------
+ // Sboxes
+ //----------------------------------------------------------------
+ aes_sbox sbox_inst0(.sboxw(sboxw0), .new_sboxw(new_sboxw0));
+ aes_sbox sbox_inst1(.sboxw(sboxw1), .new_sboxw(new_sboxw1));
+ aes_sbox sbox_inst2(.sboxw(sboxw2), .new_sboxw(new_sboxw2));
+ aes_sbox sbox_inst3(.sboxw(sboxw3), .new_sboxw(new_sboxw3));
+
+
+ //----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.