aes_speed
=========

Speed optimized Verilog implementation of the symmetric block cipher AES
(Advanced Encryption Standard) as specified in the NIST document [FIPS
197](http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf).

This core is modified version of the Cryptech AES core. Note that the
name of the core modules are identical to that core. The purpose of this
is to allow a drop-in replacement in Cryptech designs.


## Status ##
Just started, not done. Does not work.


## Introduction ##

This implementation supports 128 and 256 bit keys. The
implementation is iterative and process one 128 block at a time. Blocks
are processed on a word level with 4 S-boxes in the data path. The
S-boxes for encryption are shared with the key expansion and the core
can thus not do key update in parallel with block processing.

The encipher and decipher block processing datapaths are separated and
basically self contained given access to a set of round keys and a
block. This makes it possible to hard wire either encipher or decipher
and allow the build tools to optimize away the other functionality which
will reduce the size to about 50%. For cipher modes such as CTR, GCM
decryption in the AES core will never be used and thus the decipher
block processing can be removed.

This is a fairly compact implementation. Further reduction could be
achived by just having a single S-box. Similarly the performane can be
increased by having 8 or even 16 S-boxes which would reduce the number
of cycles to two cycles for each round.


## Performance and area comparison ##
Number of cycles for the Cryptech AES core:
- AES-128 Encipher one block with key expansion: 57


Number of cycles for the Cryptech AES speed core:
- AES-128 Encipher with key expansion: 27


Resources used by the Crypteh AES core: