From 26a85f83022fc3b3c704f037616a398e28134f8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Wed, 6 Dec 2017 14:08:14 +0100 Subject: Synced AES repo. This commit fixes many nits such as: (1) Silence warnings on size of contants. (2) warning on tasks for empty arguments in tasks. (3) timescale directives not needed. It also implements API in a code-wise more compact way. Info about implementation status updated. No changes affect the functionality of the core. --- toolruns/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'toolruns') diff --git a/toolruns/Makefile b/toolruns/Makefile index e37b2e0..ec2b413 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -51,6 +51,7 @@ TB_ENCIPHER_SRC =../src/tb/tb_aes_encipher_block.v TB_DECIPHER_SRC =../src/tb/tb_aes_decipher_block.v CC=iverilog +LINT=verilator all: top.sim core.sim keymem.sim encipher.sim decipher.sim @@ -95,6 +96,10 @@ sim-top: top.sim ./top.sim +lint: + verilator +1364-2001ext+ --lint-only -Wall $(TOP_SRC) + + clean: rm -f decipher.sim rm -f encipher.sim @@ -109,6 +114,7 @@ help: @echo "Supported targets:" @echo "------------------" @echo "all: Build all simulation targets." + @echo "lint: Lint all rtl source files." @echo "top.sim: Build top level simulation target." @echo "core.sim: Build core level simulation target." @echo "keymem.sim: Build key memory simulation target." -- cgit v1.2.3