From 833921d5f0f2c7a62594b134e6d756abd5ec012e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Wed, 3 Oct 2018 09:15:14 +0200 Subject: Adding restriction to the API to only allow writes to controlling registers. This fixes CT-01-002 FPGA. --- src/rtl/aes.v | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/rtl/aes.v b/src/rtl/aes.v index 48a7735..492ba56 100644 --- a/src/rtl/aes.v +++ b/src/rtl/aes.v @@ -225,20 +225,23 @@ module aes( begin if (we) begin - if (address == ADDR_CTRL) + if (core_ready) begin - init_new = write_data[CTRL_INIT_BIT]; - next_new = write_data[CTRL_NEXT_BIT]; - end + if (address == ADDR_CTRL) + begin + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + end - if (address == ADDR_CONFIG) - config_we = 1'b1; + if (address == ADDR_CONFIG) + config_we = 1'b1; - if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7)) - key_we = 1'b1; + if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7)) + key_we = 1'b1; - if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3)) - block_we = 1'b1; + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3)) + block_we = 1'b1; + end end // if (we) else -- cgit v1.2.3