From fd40ab87a7f13dd4ce6d636edd7bf7cffc265aa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sat, 26 May 2018 13:26:20 +0200 Subject: Shaved off another cycle for block processing. --- src/rtl/aes.v | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) (limited to 'src/rtl') diff --git a/src/rtl/aes.v b/src/rtl/aes.v index 0d719d2..ddee8f0 100644 --- a/src/rtl/aes.v +++ b/src/rtl/aes.v @@ -107,10 +107,6 @@ module aes( reg [31 : 0] key_reg [0 : 7]; reg key_we; - reg [127 : 0] result_reg; - reg valid_reg; - reg ready_reg; - //---------------------------------------------------------------- // Wires. @@ -189,16 +185,9 @@ module aes( next_reg <= 1'b0; encdec_reg <= 1'b0; keylen_reg <= 1'b0; - - result_reg <= 128'h0; - valid_reg <= 1'b0; - ready_reg <= 1'b0; end else begin - ready_reg <= core_ready; - valid_reg <= core_valid; - result_reg <= core_result; init_reg <= init_new; next_reg <= next_new; @@ -259,7 +248,7 @@ module aes( ADDR_NAME1: tmp_read_data = CORE_NAME1; ADDR_VERSION: tmp_read_data = CORE_VERSION; ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg}; - ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg}; + ADDR_STATUS: tmp_read_data = {30'h0, core_valid, core_ready}; default: begin @@ -267,7 +256,7 @@ module aes( endcase // case (address) if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3)) - tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32]; + tmp_read_data = core_result[(3 - (address - ADDR_RESULT0)) * 32 +: 32]; end end end // addr_decoder -- cgit v1.2.3