From 9af80907f9d1913cd8cb200eabe5e99cc65021a4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Thu, 27 Sep 2018 15:08:19 +0200
Subject: Added missing reset of registers. This fixes CT-01-001 FPGA.

---
 src/rtl/aes_key_mem.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/rtl')

diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
index e3aec4b..07e338f 100644
--- a/src/rtl/aes_key_mem.v
+++ b/src/rtl/aes_key_mem.v
@@ -140,12 +140,14 @@ module aes_key_mem(
 
       if (!reset_n)
         begin
-          for (i = 0 ; i < 4 ; i = i + 1)
+          for (i = 0 ; i < 15 ; i = i + 1)
             key_mem [i] <= 128'h0;
 
           rcon_reg         <= 8'h0;
           ready_reg        <= 1'b0;
           round_ctr_reg    <= 4'h0;
+          prev_key0_reg    <= 128'h0;
+          prev_key1_reg    <= 128'h0;
           key_mem_ctrl_reg <= CTRL_IDLE;
         end
       else
-- 
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