From 0361065e15bfa903aaee988b8757419a120735c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 14 Dec 2017 16:31:52 +0100 Subject: Synced the AES core rtl and testbench to github. The updates does not add or modify any functionality, but silence a lot of warnings, reduce code size. --- src/rtl/aes.v | 437 ++++++------------------------------------- src/rtl/aes_core.v | 80 ++++---- src/rtl/aes_decipher_block.v | 166 ++++++++-------- src/rtl/aes_encipher_block.v | 158 +++++++--------- src/rtl/aes_inv_sbox.v | 18 +- src/rtl/aes_key_mem.v | 168 +++++++---------- src/rtl/aes_sbox.v | 19 +- 7 files changed, 337 insertions(+), 709 deletions(-) (limited to 'src/rtl') diff --git a/src/rtl/aes.v b/src/rtl/aes.v index 043871d..c2b333a 100644 --- a/src/rtl/aes.v +++ b/src/rtl/aes.v @@ -49,8 +49,7 @@ module aes( // Data ports. input wire [7 : 0] address, input wire [31 : 0] write_data, - output wire [31 : 0] read_data, - output wire error + output wire [31 : 0] read_data ); //---------------------------------------------------------------- @@ -73,17 +72,9 @@ module aes( localparam CTRL_KEYLEN_BIT = 1; localparam ADDR_KEY0 = 8'h10; - localparam ADDR_KEY1 = 8'h11; - localparam ADDR_KEY2 = 8'h12; - localparam ADDR_KEY3 = 8'h13; - localparam ADDR_KEY4 = 8'h14; - localparam ADDR_KEY5 = 8'h15; - localparam ADDR_KEY6 = 8'h16; localparam ADDR_KEY7 = 8'h17; localparam ADDR_BLOCK0 = 8'h20; - localparam ADDR_BLOCK1 = 8'h21; - localparam ADDR_BLOCK2 = 8'h22; localparam ADDR_BLOCK3 = 8'h23; localparam ADDR_RESULT0 = 8'h30; @@ -93,7 +84,7 @@ module aes( localparam CORE_NAME0 = 32'h61657320; // "aes " localparam CORE_NAME1 = 32'h20202020; // " " - localparam CORE_VERSION = 32'h302e3830; // "0.80" + localparam CORE_VERSION = 32'h302e3630; // "0.60" //---------------------------------------------------------------- @@ -101,43 +92,19 @@ module aes( //---------------------------------------------------------------- reg init_reg; reg init_new; - reg init_we; - reg init_set; reg next_reg; reg next_new; - reg next_we; - reg next_set; reg encdec_reg; reg keylen_reg; reg config_we; - reg [31 : 0] block0_reg; - reg block0_we; - reg [31 : 0] block1_reg; - reg block1_we; - reg [31 : 0] block2_reg; - reg block2_we; - reg [31 : 0] block3_reg; - reg block3_we; - - reg [31 : 0] key0_reg; - reg key0_we; - reg [31 : 0] key1_reg; - reg key1_we; - reg [31 : 0] key2_reg; - reg key2_we; - reg [31 : 0] key3_reg; - reg key3_we; - reg [31 : 0] key4_reg; - reg key4_we; - reg [31 : 0] key5_reg; - reg key5_we; - reg [31 : 0] key6_reg; - reg key6_we; - reg [31 : 0] key7_reg; - reg key7_we; + reg [31 : 0] block_reg [0 : 3]; + reg block_we; + + reg [31 : 0] key_reg [0 : 7]; + reg key_we; reg [127 : 0] result_reg; reg valid_reg; @@ -148,7 +115,6 @@ module aes( // Wires. //---------------------------------------------------------------- reg [31 : 0] tmp_read_data; - reg tmp_error; wire core_encdec; wire core_init; @@ -165,12 +131,12 @@ module aes( // Concurrent connectivity for ports etc. //---------------------------------------------------------------- assign read_data = tmp_read_data; - assign error = tmp_error; - assign core_key = {key0_reg, key1_reg, key2_reg, key3_reg, - key4_reg, key5_reg, key6_reg, key7_reg}; + assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3], + key_reg[4], key_reg[5], key_reg[6], key_reg[7]}; - assign core_block = {block0_reg, block1_reg, block2_reg, block3_reg}; + assign core_block = {block_reg[0], block_reg[1], + block_reg[2], block_reg[3]}; assign core_init = init_reg; assign core_next = next_reg; assign core_encdec = encdec_reg; @@ -205,47 +171,33 @@ module aes( // active low reset. //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) - begin + begin : reg_update + integer i; + if (!reset_n) begin - block0_reg <= 32'h00000000; - block1_reg <= 32'h00000000; - block2_reg <= 32'h00000000; - block3_reg <= 32'h00000000; - - key0_reg <= 32'h00000000; - key1_reg <= 32'h00000000; - key2_reg <= 32'h00000000; - key3_reg <= 32'h00000000; - key4_reg <= 32'h00000000; - key5_reg <= 32'h00000000; - key6_reg <= 32'h00000000; - key7_reg <= 32'h00000000; - - init_reg <= 0; - next_reg <= 0; - encdec_reg <= 0; - keylen_reg <= 0; - - result_reg <= 128'h00000000000000000000000000000000; - valid_reg <= 0; - ready_reg <= 0; + for (i = 0 ; i < 4 ; i = i + 1) + block_reg[i] <= 32'h0; + + for (i = 0 ; i < 8 ; i = i + 1) + key_reg[i] <= 32'h0; + + init_reg <= 1'b0; + next_reg <= 1'b0; + encdec_reg <= 1'b0; + keylen_reg <= 1'b0; + + result_reg <= 128'h0; + valid_reg <= 1'b0; + ready_reg <= 1'b0; end else begin - ready_reg <= core_ready; - valid_reg <= core_valid; - result_reg <= core_result; - - if (init_we) - begin - init_reg <= init_new; - end - - if (next_we) - begin - next_reg <= next_new; - end + ready_reg <= core_ready; + valid_reg <= core_valid; + result_reg <= core_result; + init_reg <= init_new; + next_reg <= next_new; if (config_we) begin @@ -253,106 +205,15 @@ module aes( keylen_reg <= write_data[CTRL_KEYLEN_BIT]; end - if (key0_we) - begin - key0_reg <= write_data; - end - - if (key1_we) - begin - key1_reg <= write_data; - end - - if (key2_we) - begin - key2_reg <= write_data; - end - - if (key3_we) - begin - key3_reg <= write_data; - end - - if (key4_we) - begin - key4_reg <= write_data; - end - - if (key5_we) - begin - key5_reg <= write_data; - end - - if (key6_we) - begin - key6_reg <= write_data; - end - - if (key7_we) - begin - key7_reg <= write_data; - end - - if (block0_we) - begin - block0_reg <= write_data; - end - - if (block1_we) - begin - block1_reg <= write_data; - end - - if (block2_we) - begin - block2_reg <= write_data; - end + if (key_we) + key_reg[address[2 : 0]] <= write_data; - if (block3_we) - begin - block3_reg <= write_data; - end + if (block_we) + block_reg[address[1 : 0]] <= write_data; end end // reg_update - //---------------------------------------------------------------- - // flag_ctrl - // - // Logic to set and automatically reset init- and next - // flags that has been set. - //---------------------------------------------------------------- - always @* - begin : flag_reset - init_new = 0; - init_we = 0; - next_new = 0; - next_we = 0; - - if (init_set) - begin - init_new = 1; - init_we = 1; - end - else if (init_reg) - begin - init_new = 0; - init_we = 1; - end - - if (next_set) - begin - next_new = 1; - next_we = 1; - end - else if (next_reg) - begin - next_new = 0; - next_we = 1; - end - end - - //---------------------------------------------------------------- // api // @@ -360,223 +221,49 @@ module aes( //---------------------------------------------------------------- always @* begin : api - init_set = 0; - next_set = 0; - config_we = 0; - key0_we = 0; - key1_we = 0; - key2_we = 0; - key3_we = 0; - key4_we = 0; - key5_we = 0; - key6_we = 0; - key7_we = 0; - block0_we = 0; - block1_we = 0; - block2_we = 0; - block3_we = 0; - tmp_read_data = 32'h00000000; - tmp_error = 0; + init_new = 1'b0; + next_new = 1'b0; + config_we = 1'b0; + key_we = 1'b0; + block_we = 1'b0; + tmp_read_data = 32'h0; if (cs) begin if (we) begin - case (address) - // Write operations. - ADDR_CTRL: - begin - init_set = write_data[CTRL_INIT_BIT]; - next_set = write_data[CTRL_NEXT_BIT]; - end - - ADDR_CONFIG: - begin - config_we = 1; - end - - ADDR_KEY0: - begin - key0_we = 1; - end - - ADDR_KEY1: - begin - key1_we = 1; - end - - ADDR_KEY2: - begin - key2_we = 1; - end - - ADDR_KEY3: - begin - key3_we = 1; - end - - ADDR_KEY4: - begin - key4_we = 1; - end - - ADDR_KEY5: - begin - key5_we = 1; - end - - ADDR_KEY6: - begin - key6_we = 1; - end + if (address == ADDR_CTRL) + begin + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + end - ADDR_KEY7: - begin - key7_we = 1; - end + if (address == ADDR_CONFIG) + config_we = 1'b1; - ADDR_BLOCK0: - begin - block0_we = 1; - end - - ADDR_BLOCK1: - begin - block1_we = 1; - end + if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7)) + key_we = 1'b1; - ADDR_BLOCK2: - begin - block2_we = 1; - end - - ADDR_BLOCK3: - begin - block3_we = 1; - end - - default: - begin - tmp_error = 1; - end - endcase // case (address) + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3)) + block_we = 1'b1; end // if (we) else begin case (address) - // Read operations. - ADDR_NAME0: - begin - tmp_read_data = CORE_NAME0; - end - - ADDR_NAME1: - begin - tmp_read_data = CORE_NAME1; - end - - ADDR_VERSION: - begin - tmp_read_data = CORE_VERSION; - end - - ADDR_CTRL: - begin - tmp_read_data = {28'h0000000, keylen_reg, encdec_reg, - next_reg, init_reg}; - end - - ADDR_STATUS: - begin - tmp_read_data = {30'h00000000, valid_reg, ready_reg}; - end - - ADDR_KEY0: - begin - tmp_read_data = key0_reg; - end - - ADDR_KEY1: - begin - tmp_read_data = key1_reg; - end - - ADDR_KEY2: - begin - tmp_read_data = key2_reg; - end - - ADDR_KEY3: - begin - tmp_read_data = key3_reg; - end - - ADDR_KEY4: - begin - tmp_read_data = key4_reg; - end - - ADDR_KEY5: - begin - tmp_read_data = key5_reg; - end - - ADDR_KEY6: - begin - tmp_read_data = key6_reg; - end - - ADDR_KEY7: - begin - tmp_read_data = key7_reg; - end - - ADDR_BLOCK0: - begin - tmp_read_data = block0_reg; - end - - ADDR_BLOCK1: - begin - tmp_read_data = block1_reg; - end - - ADDR_BLOCK2: - begin - tmp_read_data = block2_reg; - end - - ADDR_BLOCK3: - begin - tmp_read_data = block3_reg; - end - - ADDR_RESULT0: - begin - tmp_read_data = result_reg[127 : 96]; - end - - ADDR_RESULT1: - begin - tmp_read_data = result_reg[95 : 64]; - end - - ADDR_RESULT2: - begin - tmp_read_data = result_reg[63 : 32]; - end - - ADDR_RESULT3: - begin - tmp_read_data = result_reg[31 : 0]; - end + ADDR_NAME0: tmp_read_data = CORE_NAME0; + ADDR_NAME1: tmp_read_data = CORE_NAME1; + ADDR_VERSION: tmp_read_data = CORE_VERSION; + ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg}; + ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg}; default: begin - tmp_error = 1; end endcase // case (address) + + if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3)) + tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32]; end end end // addr_decoder diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v index 0eb10a4..5196a1f 100644 --- a/src/rtl/aes_core.v +++ b/src/rtl/aes_core.v @@ -61,9 +61,9 @@ module aes_core( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter CTRL_IDLE = 2'h0; - parameter CTRL_INIT = 2'h1; - parameter CTRL_NEXT = 2'h2; + localparam CTRL_IDLE = 2'h0; + localparam CTRL_INIT = 2'h1; + localparam CTRL_NEXT = 2'h2; //---------------------------------------------------------------- @@ -166,7 +166,7 @@ module aes_core( ); - aes_sbox sbox(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw)); + aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw)); //---------------------------------------------------------------- @@ -195,19 +195,13 @@ module aes_core( else begin if (result_valid_we) - begin - result_valid_reg <= result_valid_new; - end + result_valid_reg <= result_valid_new; if (ready_we) - begin - ready_reg <= ready_new; - end + ready_reg <= ready_new; if (aes_core_ctrl_we) - begin - aes_core_ctrl_reg <= aes_core_ctrl_new; - end + aes_core_ctrl_reg <= aes_core_ctrl_new; end end // reg_update @@ -239,8 +233,8 @@ module aes_core( //---------------------------------------------------------------- always @* begin : encdec_mux - enc_next = 0; - dec_next = 0; + enc_next = 1'b0; + dec_next = 1'b0; if (encdec) begin @@ -270,64 +264,64 @@ module aes_core( //---------------------------------------------------------------- always @* begin : aes_core_ctrl - init_state = 0; - ready_new = 0; - ready_we = 0; - result_valid_new = 0; - result_valid_we = 0; + init_state = 1'b0; + ready_new = 1'b0; + ready_we = 1'b0; + result_valid_new = 1'b0; + result_valid_we = 1'b0; aes_core_ctrl_new = CTRL_IDLE; - aes_core_ctrl_we = 0; + aes_core_ctrl_we = 1'b0; case (aes_core_ctrl_reg) CTRL_IDLE: begin if (init) begin - init_state = 1; - ready_new = 0; - ready_we = 1; - result_valid_new = 0; - result_valid_we = 1; + init_state = 1'b1; + ready_new = 1'b0; + ready_we = 1'b1; + result_valid_new = 1'b0; + result_valid_we = 1'b1; aes_core_ctrl_new = CTRL_INIT; - aes_core_ctrl_we = 1; + aes_core_ctrl_we = 1'b1; end else if (next) begin - init_state = 0; - ready_new = 0; - ready_we = 1; - result_valid_new = 0; - result_valid_we = 1; + init_state = 1'b0; + ready_new = 1'b0; + ready_we = 1'b1; + result_valid_new = 1'b0; + result_valid_we = 1'b1; aes_core_ctrl_new = CTRL_NEXT; - aes_core_ctrl_we = 1; + aes_core_ctrl_we = 1'b1; end end CTRL_INIT: begin - init_state = 1; + init_state = 1'b1; if (key_ready) begin - ready_new = 1; - ready_we = 1; + ready_new = 1'b1; + ready_we = 1'b1; aes_core_ctrl_new = CTRL_IDLE; - aes_core_ctrl_we = 1; + aes_core_ctrl_we = 1'b1; end end CTRL_NEXT: begin - init_state = 0; + init_state = 1'b0; if (muxed_ready) begin - ready_new = 1; - ready_we = 1; - result_valid_new = 1; - result_valid_we = 1; + ready_new = 1'b1; + ready_we = 1'b1; + result_valid_new = 1'b1; + result_valid_we = 1'b1; aes_core_ctrl_new = CTRL_IDLE; - aes_core_ctrl_we = 1; + aes_core_ctrl_we = 1'b1; end end diff --git a/src/rtl/aes_decipher_block.v b/src/rtl/aes_decipher_block.v index 75da9fb..82bdffb 100644 --- a/src/rtl/aes_decipher_block.v +++ b/src/rtl/aes_decipher_block.v @@ -58,23 +58,23 @@ module aes_decipher_block( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter AES_128_BIT_KEY = 1'h0; - parameter AES_256_BIT_KEY = 1'h1; + localparam AES_128_BIT_KEY = 1'h0; + localparam AES_256_BIT_KEY = 1'h1; - parameter AES128_ROUNDS = 4'ha; - parameter AES256_ROUNDS = 4'he; + localparam AES128_ROUNDS = 4'ha; + localparam AES256_ROUNDS = 4'he; - parameter NO_UPDATE = 3'h0; - parameter INIT_UPDATE = 3'h1; - parameter SBOX_UPDATE = 3'h2; - parameter MAIN_UPDATE = 3'h3; - parameter FINAL_UPDATE = 3'h4; + localparam NO_UPDATE = 3'h0; + localparam INIT_UPDATE = 3'h1; + localparam SBOX_UPDATE = 3'h2; + localparam MAIN_UPDATE = 3'h3; + localparam FINAL_UPDATE = 3'h4; - parameter CTRL_IDLE = 3'h0; - parameter CTRL_INIT = 3'h1; - parameter CTRL_SBOX = 3'h2; - parameter CTRL_MAIN = 3'h3; - parameter CTRL_FINAL = 3'h4; + localparam CTRL_IDLE = 3'h0; + localparam CTRL_INIT = 3'h1; + localparam CTRL_SBOX = 3'h2; + localparam CTRL_MAIN = 3'h3; + localparam CTRL_FINAL = 3'h4; //---------------------------------------------------------------- @@ -229,13 +229,12 @@ module aes_decipher_block( reg [31 : 0] tmp_sboxw; wire [31 : 0] new_sboxw; reg [2 : 0] update_type; - reg [3 : 0] num_rounds; //---------------------------------------------------------------- // Instantiations. //---------------------------------------------------------------- - aes_inv_sbox inv_sbox(.sword(tmp_sboxw), .new_sword(new_sboxw)); + aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw)); //---------------------------------------------------------------- @@ -257,56 +256,40 @@ module aes_decipher_block( begin: reg_update if (!reset_n) begin - block_w0_reg <= 32'h00000000; - block_w1_reg <= 32'h00000000; - block_w2_reg <= 32'h00000000; - block_w3_reg <= 32'h00000000; + block_w0_reg <= 32'h0; + block_w1_reg <= 32'h0; + block_w2_reg <= 32'h0; + block_w3_reg <= 32'h0; sword_ctr_reg <= 2'h0; round_ctr_reg <= 4'h0; - ready_reg <= 1; + ready_reg <= 1'b1; dec_ctrl_reg <= CTRL_IDLE; end else begin if (block_w0_we) - begin - block_w0_reg <= block_new[127 : 096]; - end + block_w0_reg <= block_new[127 : 096]; if (block_w1_we) - begin - block_w1_reg <= block_new[095 : 064]; - end + block_w1_reg <= block_new[095 : 064]; if (block_w2_we) - begin - block_w2_reg <= block_new[063 : 032]; - end + block_w2_reg <= block_new[063 : 032]; if (block_w3_we) - begin - block_w3_reg <= block_new[031 : 000]; - end + block_w3_reg <= block_new[031 : 000]; if (sword_ctr_we) - begin - sword_ctr_reg <= sword_ctr_new; - end + sword_ctr_reg <= sword_ctr_new; if (round_ctr_we) - begin - round_ctr_reg <= round_ctr_new; - end + round_ctr_reg <= round_ctr_new; if (ready_we) - begin - ready_reg <= ready_new; - end + ready_reg <= ready_new; if (dec_ctrl_we) - begin - dec_ctrl_reg <= dec_ctrl_new; - end + dec_ctrl_reg <= dec_ctrl_new; end end // reg_update @@ -321,15 +304,15 @@ module aes_decipher_block( reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block; reg [127 : 0] addkey_block; - inv_shiftrows_block = 128'h00000000000000000000000000000000; - inv_mixcolumns_block = 128'h00000000000000000000000000000000; - addkey_block = 128'h00000000000000000000000000000000; - block_new = 128'h00000000000000000000000000000000; - tmp_sboxw = 32'h00000000; - block_w0_we = 0; - block_w1_we = 0; - block_w2_we = 0; - block_w3_we = 0; + inv_shiftrows_block = 128'h0; + inv_mixcolumns_block = 128'h0; + addkey_block = 128'h0; + block_new = 128'h0; + tmp_sboxw = 32'h0; + block_w0_we = 1'b0; + block_w1_we = 1'b0; + block_w2_we = 1'b0; + block_w3_we = 1'b0; old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg}; @@ -342,10 +325,10 @@ module aes_decipher_block( addkey_block = addroundkey(old_block, round_key); inv_shiftrows_block = inv_shiftrows(addkey_block); block_new = inv_shiftrows_block; - block_w0_we = 1; - block_w1_we = 1; - block_w2_we = 1; - block_w3_we = 1; + block_w0_we = 1'b1; + block_w1_we = 1'b1; + block_w2_we = 1'b1; + block_w3_we = 1'b1; end SBOX_UPDATE: @@ -356,25 +339,25 @@ module aes_decipher_block( 2'h0: begin tmp_sboxw = block_w0_reg; - block_w0_we = 1; + block_w0_we = 1'b1; end 2'h1: begin tmp_sboxw = block_w1_reg; - block_w1_we = 1; + block_w1_we = 1'b1; end 2'h2: begin tmp_sboxw = block_w2_reg; - block_w2_we = 1; + block_w2_we = 1'b1; end 2'h3: begin tmp_sboxw = block_w3_reg; - block_w3_we = 1; + block_w3_we = 1'b1; end endcase // case (sbox_mux_ctrl_reg) end @@ -385,19 +368,19 @@ module aes_decipher_block( inv_mixcolumns_block = inv_mixcolumns(addkey_block); inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block); block_new = inv_shiftrows_block; - block_w0_we = 1; - block_w1_we = 1; - block_w2_we = 1; - block_w3_we = 1; + block_w0_we = 1'b1; + block_w1_we = 1'b1; + block_w2_we = 1'b1; + block_w3_we = 1'b1; end FINAL_UPDATE: begin block_new = addroundkey(old_block, round_key); - block_w0_we = 1; - block_w1_we = 1; - block_w2_we = 1; - block_w3_we = 1; + block_w0_we = 1'b1; + block_w1_we = 1'b1; + block_w2_we = 1'b1; + block_w3_we = 1'b1; end default: @@ -467,65 +450,65 @@ module aes_decipher_block( //---------------------------------------------------------------- always @* begin: decipher_ctrl - sword_ctr_inc = 0; - sword_ctr_rst = 0; - round_ctr_dec = 0; - round_ctr_set = 0; - ready_new = 0; - ready_we = 0; + sword_ctr_inc = 1'b0; + sword_ctr_rst = 1'b0; + round_ctr_dec = 1'b0; + round_ctr_set = 1'b0; + ready_new = 1'b0; + ready_we = 1'b0; update_type = NO_UPDATE; dec_ctrl_new = CTRL_IDLE; - dec_ctrl_we = 0; + dec_ctrl_we = 1'b0; case(dec_ctrl_reg) CTRL_IDLE: begin if (next) begin - round_ctr_set = 1; - ready_new = 0; - ready_we = 1; + round_ctr_set = 1'b1; + ready_new = 1'b0; + ready_we = 1'b1; dec_ctrl_new = CTRL_INIT; - dec_ctrl_we = 1; + dec_ctrl_we = 1'b1; end end CTRL_INIT: begin - sword_ctr_rst = 1; + sword_ctr_rst = 1'b1; update_type = INIT_UPDATE; dec_ctrl_new = CTRL_SBOX; - dec_ctrl_we = 1; + dec_ctrl_we = 1'b1; end CTRL_SBOX: begin - sword_ctr_inc = 1; + sword_ctr_inc = 1'b1; update_type = SBOX_UPDATE; if (sword_ctr_reg == 2'h3) begin - round_ctr_dec = 1; + round_ctr_dec = 1'b1; dec_ctrl_new = CTRL_MAIN; - dec_ctrl_we = 1; + dec_ctrl_we = 1'b1; end end CTRL_MAIN: begin - sword_ctr_rst = 1; + sword_ctr_rst = 1'b1; if (round_ctr_reg > 0) begin update_type = MAIN_UPDATE; dec_ctrl_new = CTRL_SBOX; - dec_ctrl_we = 1; + dec_ctrl_we = 1'b1; end else begin update_type = FINAL_UPDATE; - ready_new = 1; - ready_we = 1; + ready_new = 1'b1; + ready_we = 1'b1; dec_ctrl_new = CTRL_IDLE; - dec_ctrl_we = 1; + dec_ctrl_we = 1'b1; end end @@ -535,7 +518,6 @@ module aes_decipher_block( end endcase // case (dec_ctrl_reg) end // decipher_ctrl - endmodule // aes_decipher_block //====================================================================== diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v index 1990c0b..094653a 100644 --- a/src/rtl/aes_encipher_block.v +++ b/src/rtl/aes_encipher_block.v @@ -61,23 +61,23 @@ module aes_encipher_block( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter AES_128_BIT_KEY = 1'h0; - parameter AES_256_BIT_KEY = 1'h1; + localparam AES_128_BIT_KEY = 1'h0; + localparam AES_256_BIT_KEY = 1'h1; - parameter AES128_ROUNDS = 4'ha; - parameter AES256_ROUNDS = 4'he; + localparam AES128_ROUNDS = 4'ha; + localparam AES256_ROUNDS = 4'he; - parameter NO_UPDATE = 3'h0; - parameter INIT_UPDATE = 3'h1; - parameter SBOX_UPDATE = 3'h2; - parameter MAIN_UPDATE = 3'h3; - parameter FINAL_UPDATE = 3'h4; + localparam NO_UPDATE = 3'h0; + localparam INIT_UPDATE = 3'h1; + localparam SBOX_UPDATE = 3'h2; + localparam MAIN_UPDATE = 3'h3; + localparam FINAL_UPDATE = 3'h4; - parameter CTRL_IDLE = 3'h0; - parameter CTRL_INIT = 3'h1; - parameter CTRL_SBOX = 3'h2; - parameter CTRL_MAIN = 3'h3; - parameter CTRL_FINAL = 3'h4; + localparam CTRL_IDLE = 3'h0; + localparam CTRL_INIT = 3'h1; + localparam CTRL_SBOX = 3'h2; + localparam CTRL_MAIN = 3'h3; + localparam CTRL_FINAL = 3'h4; //---------------------------------------------------------------- @@ -217,56 +217,40 @@ module aes_encipher_block( begin: reg_update if (!reset_n) begin - block_w0_reg <= 32'h00000000; - block_w1_reg <= 32'h00000000; - block_w2_reg <= 32'h00000000; - block_w3_reg <= 32'h00000000; + block_w0_reg <= 32'h0; + block_w1_reg <= 32'h0; + block_w2_reg <= 32'h0; + block_w3_reg <= 32'h0; sword_ctr_reg <= 2'h0; round_ctr_reg <= 4'h0; - ready_reg <= 1; + ready_reg <= 1'b1; enc_ctrl_reg <= CTRL_IDLE; end else begin if (block_w0_we) - begin - block_w0_reg <= block_new[127 : 096]; - end + block_w0_reg <= block_new[127 : 096]; if (block_w1_we) - begin - block_w1_reg <= block_new[095 : 064]; - end + block_w1_reg <= block_new[095 : 064]; if (block_w2_we) - begin - block_w2_reg <= block_new[063 : 032]; - end + block_w2_reg <= block_new[063 : 032]; if (block_w3_we) - begin - block_w3_reg <= block_new[031 : 000]; - end + block_w3_reg <= block_new[031 : 000]; if (sword_ctr_we) - begin - sword_ctr_reg <= sword_ctr_new; - end + sword_ctr_reg <= sword_ctr_new; if (round_ctr_we) - begin - round_ctr_reg <= round_ctr_new; - end + round_ctr_reg <= round_ctr_new; if (ready_we) - begin - ready_reg <= ready_new; - end + ready_reg <= ready_new; if (enc_ctrl_we) - begin - enc_ctrl_reg <= enc_ctrl_new; - end + enc_ctrl_reg <= enc_ctrl_new; end end // reg_update @@ -281,12 +265,12 @@ module aes_encipher_block( reg [127 : 0] old_block, shiftrows_block, mixcolumns_block; reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block; - block_new = 128'h00000000000000000000000000000000; - muxed_sboxw = 32'h00000000; - block_w0_we = 0; - block_w1_we = 0; - block_w2_we = 0; - block_w3_we = 0; + block_new = 128'h0; + muxed_sboxw = 32'h0; + block_w0_we = 1'b0; + block_w1_we = 1'b0; + block_w2_we = 1'b0; + block_w3_we = 1'b0; old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg}; shiftrows_block = shiftrows(old_block); @@ -299,10 +283,10 @@ module aes_encipher_block( INIT_UPDATE: begin block_new = addkey_init_block; - block_w0_we = 1; - block_w1_we = 1; - block_w2_we = 1; - block_w3_we = 1; + block_w0_we = 1'b1; + block_w1_we = 1'b1; + block_w2_we = 1'b1; + block_w3_we = 1'b1; end SBOX_UPDATE: @@ -313,25 +297,25 @@ module aes_encipher_block( 2'h0: begin muxed_sboxw = block_w0_reg; - block_w0_we = 1; + block_w0_we = 1'b1; end 2'h1: begin muxed_sboxw = block_w1_reg; - block_w1_we = 1; + block_w1_we = 1'b1; end 2'h2: begin muxed_sboxw = block_w2_reg; - block_w2_we = 1; + block_w2_we = 1'b1; end 2'h3: begin muxed_sboxw = block_w3_reg; - block_w3_we = 1; + block_w3_we = 1'b1; end endcase // case (sbox_mux_ctrl_reg) end @@ -339,19 +323,19 @@ module aes_encipher_block( MAIN_UPDATE: begin block_new = addkey_main_block; - block_w0_we = 1; - block_w1_we = 1; - block_w2_we = 1; - block_w3_we = 1; + block_w0_we = 1'b1; + block_w1_we = 1'b1; + block_w2_we = 1'b1; + block_w3_we = 1'b1; end FINAL_UPDATE: begin block_new = addkey_final_block; - block_w0_we = 1; - block_w1_we = 1; - block_w2_we = 1; - block_w3_we = 1; + block_w0_we = 1'b1; + block_w1_we = 1'b1; + block_w2_we = 1'b1; + block_w3_we = 1'b1; end default: @@ -425,66 +409,66 @@ module aes_encipher_block( num_rounds = AES128_ROUNDS; end - sword_ctr_inc = 0; - sword_ctr_rst = 0; - round_ctr_inc = 0; - round_ctr_rst = 0; - ready_new = 0; - ready_we = 0; + sword_ctr_inc = 1'b0; + sword_ctr_rst = 1'b0; + round_ctr_inc = 1'b0; + round_ctr_rst = 1'b0; + ready_new = 1'b0; + ready_we = 1'b0; update_type = NO_UPDATE; enc_ctrl_new = CTRL_IDLE; - enc_ctrl_we = 0; + enc_ctrl_we = 1'b0; case(enc_ctrl_reg) CTRL_IDLE: begin if (next) begin - round_ctr_rst = 1; - ready_new = 0; - ready_we = 1; + round_ctr_rst = 1'b1; + ready_new = 1'b0; + ready_we = 1'b1; enc_ctrl_new = CTRL_INIT; - enc_ctrl_we = 1; + enc_ctrl_we = 1'b1; end end CTRL_INIT: begin - round_ctr_inc = 1; - sword_ctr_rst = 1; + round_ctr_inc = 1'b1; + sword_ctr_rst = 1'b1; update_type = INIT_UPDATE; enc_ctrl_new = CTRL_SBOX; - enc_ctrl_we = 1; + enc_ctrl_we = 1'b1; end CTRL_SBOX: begin - sword_ctr_inc = 1; + sword_ctr_inc = 1'b1; update_type = SBOX_UPDATE; if (sword_ctr_reg == 2'h3) begin enc_ctrl_new = CTRL_MAIN; - enc_ctrl_we = 1; + enc_ctrl_we = 1'b1; end end CTRL_MAIN: begin - sword_ctr_rst = 1; - round_ctr_inc = 1; + sword_ctr_rst = 1'b1; + round_ctr_inc = 1'b1; if (round_ctr_reg < num_rounds) begin update_type = MAIN_UPDATE; enc_ctrl_new = CTRL_SBOX; - enc_ctrl_we = 1; + enc_ctrl_we = 1'b1; end else begin update_type = FINAL_UPDATE; - ready_new = 1; - ready_we = 1; + ready_new = 1'b1; + ready_we = 1'b1; enc_ctrl_new = CTRL_IDLE; - enc_ctrl_we = 1; + enc_ctrl_we = 1'b1; end end diff --git a/src/rtl/aes_inv_sbox.v b/src/rtl/aes_inv_sbox.v index 68642db..807f397 100644 --- a/src/rtl/aes_inv_sbox.v +++ b/src/rtl/aes_inv_sbox.v @@ -44,13 +44,22 @@ module aes_inv_sbox( //---------------------------------------------------------------- - // Wires. + // The inverse sbox array. //---------------------------------------------------------------- wire [7 : 0] inv_sbox [0 : 255]; //---------------------------------------------------------------- - // Concurrent assignments for ports. + // Four parallel muxes. + //---------------------------------------------------------------- + assign new_sword[31 : 24] = inv_sbox[sword[31 : 24]]; + assign new_sword[23 : 16] = inv_sbox[sword[23 : 16]]; + assign new_sword[15 : 08] = inv_sbox[sword[15 : 08]]; + assign new_sword[07 : 00] = inv_sbox[sword[07 : 00]]; + + + //---------------------------------------------------------------- + // Creating the contents of the array. //---------------------------------------------------------------- assign inv_sbox[8'h00] = 8'h52; assign inv_sbox[8'h01] = 8'h09; @@ -309,11 +318,6 @@ module aes_inv_sbox( assign inv_sbox[8'hfe] = 8'h0c; assign inv_sbox[8'hff] = 8'h7d; - assign new_sword[31 : 24] = inv_sbox[sword[31 : 24]]; - assign new_sword[23 : 16] = inv_sbox[sword[23 : 16]]; - assign new_sword[15 : 08] = inv_sbox[sword[15 : 08]]; - assign new_sword[07 : 00] = inv_sbox[sword[07 : 00]]; - endmodule // aes_inv_sbox //====================================================================== diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v index f6cb3af..496fc08 100644 --- a/src/rtl/aes_key_mem.v +++ b/src/rtl/aes_key_mem.v @@ -58,16 +58,16 @@ module aes_key_mem( //---------------------------------------------------------------- // Parameters. //---------------------------------------------------------------- - parameter AES_128_BIT_KEY = 1'h0; - parameter AES_256_BIT_KEY = 1'h1; + localparam AES_128_BIT_KEY = 1'h0; + localparam AES_256_BIT_KEY = 1'h1; - parameter AES_128_NUM_ROUNDS = 4'ha; - parameter AES_256_NUM_ROUNDS = 4'he; + localparam AES_128_NUM_ROUNDS = 4'ha; + localparam AES_256_NUM_ROUNDS = 4'he; - parameter CTRL_IDLE = 3'h0; - parameter CTRL_INIT = 3'h1; - parameter CTRL_GENERATE = 3'h2; - parameter CTRL_DONE = 3'h3; + localparam CTRL_IDLE = 3'h0; + localparam CTRL_INIT = 3'h1; + localparam CTRL_GENERATE = 3'h2; + localparam CTRL_DONE = 3'h3; //---------------------------------------------------------------- @@ -134,66 +134,40 @@ module aes_key_mem( //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin: reg_update + integer i; + if (!reset_n) begin - key_mem [0] <= 128'h00000000000000000000000000000000; - key_mem [1] <= 128'h00000000000000000000000000000000; - key_mem [2] <= 128'h00000000000000000000000000000000; - key_mem [3] <= 128'h00000000000000000000000000000000; - key_mem [4] <= 128'h00000000000000000000000000000000; - key_mem [5] <= 128'h00000000000000000000000000000000; - key_mem [6] <= 128'h00000000000000000000000000000000; - key_mem [7] <= 128'h00000000000000000000000000000000; - key_mem [8] <= 128'h00000000000000000000000000000000; - key_mem [9] <= 128'h00000000000000000000000000000000; - key_mem [10] <= 128'h00000000000000000000000000000000; - key_mem [11] <= 128'h00000000000000000000000000000000; - key_mem [12] <= 128'h00000000000000000000000000000000; - key_mem [13] <= 128'h00000000000000000000000000000000; - key_mem [14] <= 128'h00000000000000000000000000000000; - prev_key0_reg <= 128'h00000000000000000000000000000000; - prev_key1_reg <= 128'h00000000000000000000000000000000; - rcon_reg <= 8'h00; - ready_reg <= 0; + for (i = 0 ; i < 4 ; i = i + 1) + key_mem [i] <= 128'h0; + + rcon_reg <= 8'h0; + ready_reg <= 1'b0; round_ctr_reg <= 4'h0; key_mem_ctrl_reg <= CTRL_IDLE; end else begin if (round_ctr_we) - begin - round_ctr_reg <= round_ctr_new; - end + round_ctr_reg <= round_ctr_new; if (ready_we) - begin - ready_reg <= ready_new; - end + ready_reg <= ready_new; if (rcon_we) - begin - rcon_reg <= rcon_new; - end + rcon_reg <= rcon_new; if (key_mem_we) - begin - key_mem[round_ctr_reg] <= key_mem_new; - end + key_mem[round_ctr_reg] <= key_mem_new; if (prev_key0_we) - begin - prev_key0_reg <= prev_key0_new; - end + prev_key0_reg <= prev_key0_new; if (prev_key1_we) - begin - prev_key1_reg <= prev_key1_new; - end + prev_key1_reg <= prev_key1_new; if (key_mem_ctrl_we) - begin - key_mem_ctrl_reg <= key_mem_ctrl_new; - end + key_mem_ctrl_reg <= key_mem_ctrl_new; end end // reg_update @@ -221,20 +195,20 @@ module aes_key_mem( reg [31 : 0] rconw, rotstw, tw, trw; // Default assignments. - key_mem_new = 128'h00000000000000000000000000000000; - key_mem_we = 0; - prev_key0_new = 128'h00000000000000000000000000000000; - prev_key0_we = 0; - prev_key1_new = 128'h00000000000000000000000000000000; - prev_key1_we = 0; + key_mem_new = 128'h0; + key_mem_we = 1'b0; + prev_key0_new = 128'h0; + prev_key0_we = 1'b0; + prev_key1_new = 128'h0; + prev_key1_we = 1'b0; - k0 = 32'h00000000; - k1 = 32'h00000000; - k2 = 32'h00000000; - k3 = 32'h00000000; + k0 = 32'h0; + k1 = 32'h0; + k2 = 32'h0; + k3 = 32'h0; - rcon_set = 1; - rcon_next = 0; + rcon_set = 1'b1; + rcon_next = 1'b0; // Extract words and calculate intermediate values. // Perform rotation of sbox word etc. @@ -248,7 +222,7 @@ module aes_key_mem( w6 = prev_key1_reg[063 : 032]; w7 = prev_key1_reg[031 : 000]; - rconw = {rcon_reg, 24'h000000}; + rconw = {rcon_reg, 24'h0}; tmp_sboxw = w7; rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]}; trw = rotstw ^ rconw; @@ -257,8 +231,8 @@ module aes_key_mem( // Generate the specific round keys. if (round_key_update) begin - rcon_set = 0; - key_mem_we = 1; + rcon_set = 1'b0; + key_mem_we = 1'b1; case (keylen) AES_128_BIT_KEY: begin @@ -266,8 +240,8 @@ module aes_key_mem( begin key_mem_new = key[255 : 128]; prev_key1_new = key[255 : 128]; - prev_key1_we = 1; - rcon_next = 1; + prev_key1_we = 1'b1; + rcon_next = 1'b1; end else begin @@ -278,8 +252,8 @@ module aes_key_mem( key_mem_new = {k0, k1, k2, k3}; prev_key1_new = {k0, k1, k2, k3}; - prev_key1_we = 1; - rcon_next = 1; + prev_key1_we = 1'b1; + rcon_next = 1'b1; end end @@ -289,14 +263,14 @@ module aes_key_mem( begin key_mem_new = key[255 : 128]; prev_key0_new = key[255 : 128]; - prev_key0_we = 1; + prev_key0_we = 1'b1; end else if (round_ctr_reg == 1) begin key_mem_new = key[127 : 0]; prev_key1_new = key[127 : 0]; - prev_key1_we = 1; - rcon_next = 1; + prev_key1_we = 1'b1; + rcon_next = 1'b1; end else begin @@ -313,15 +287,15 @@ module aes_key_mem( k1 = w1 ^ w0 ^ tw; k2 = w2 ^ w1 ^ w0 ^ tw; k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw; - rcon_next = 1; + rcon_next = 1'b1; end // Store the generated round keys. key_mem_new = {k0, k1, k2, k3}; prev_key1_new = {k0, k1, k2, k3}; - prev_key1_we = 1; + prev_key1_we = 1'b1; prev_key0_new = prev_key1_reg; - prev_key0_we = 1; + prev_key0_we = 1'b1; end end @@ -343,20 +317,20 @@ module aes_key_mem( begin : rcon_logic reg [7 : 0] tmp_rcon; rcon_new = 8'h00; - rcon_we = 0; + rcon_we = 1'b0; tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}}); if (rcon_set) begin rcon_new = 8'h8d; - rcon_we = 1; + rcon_we = 1'b1; end if (rcon_next) begin - rcon_new = tmp_rcon[7 : 0]; - rcon_we = 1; + rcon_new = tmp_rcon[7 : 0]; + rcon_we = 1'b1; end end @@ -369,18 +343,18 @@ module aes_key_mem( always @* begin : round_ctr round_ctr_new = 4'h0; - round_ctr_we = 0; + round_ctr_we = 1'b0; if (round_ctr_rst) begin round_ctr_new = 4'h0; - round_ctr_we = 1; + round_ctr_we = 1'b1; end else if (round_ctr_inc) begin round_ctr_new = round_ctr_reg + 1'b1; - round_ctr_we = 1; + round_ctr_we = 1'b1; end end @@ -421,50 +395,50 @@ module aes_key_mem( always @* begin: key_mem_ctrl // Default assignments. - ready_new = 0; - ready_we = 0; - round_key_update = 0; - round_ctr_rst = 0; - round_ctr_inc = 0; + ready_new = 1'b0; + ready_we = 1'b0; + round_key_update = 1'b0; + round_ctr_rst = 1'b0; + round_ctr_inc = 1'b0; key_mem_ctrl_new = CTRL_IDLE; - key_mem_ctrl_we = 0; + key_mem_ctrl_we = 1'b0; case(key_mem_ctrl_reg) CTRL_IDLE: begin if (init) begin - ready_new = 0; - ready_we = 1; + ready_new = 1'b0; + ready_we = 1'b1; key_mem_ctrl_new = CTRL_INIT; - key_mem_ctrl_we = 1; + key_mem_ctrl_we = 1'b1; end end CTRL_INIT: begin - round_ctr_rst = 1; + round_ctr_rst = 1'b1; key_mem_ctrl_new = CTRL_GENERATE; - key_mem_ctrl_we = 1; + key_mem_ctrl_we = 1'b1; end CTRL_GENERATE: begin - round_ctr_inc = 1; - round_key_update = 1; + round_ctr_inc = 1'b1; + round_key_update = 1'b1; if (round_ctr_reg == num_rounds) begin key_mem_ctrl_new = CTRL_DONE; - key_mem_ctrl_we = 1; + key_mem_ctrl_we = 1'b1; end end CTRL_DONE: begin - ready_new = 1; - ready_we = 1; + ready_new = 1'b1; + ready_we = 1'b1; key_mem_ctrl_new = CTRL_IDLE; - key_mem_ctrl_we = 1; + key_mem_ctrl_we = 1'b1; end default: diff --git a/src/rtl/aes_sbox.v b/src/rtl/aes_sbox.v index 84ff6a9..09ba129 100644 --- a/src/rtl/aes_sbox.v +++ b/src/rtl/aes_sbox.v @@ -44,13 +44,22 @@ module aes_sbox( //---------------------------------------------------------------- - // Wires. + // The sbox array. //---------------------------------------------------------------- wire [7 : 0] sbox [0 : 255]; //---------------------------------------------------------------- - // Concurrent assignments for ports. + // Four parallel muxes. + //---------------------------------------------------------------- + assign new_sboxw[31 : 24] = sbox[sboxw[31 : 24]]; + assign new_sboxw[23 : 16] = sbox[sboxw[23 : 16]]; + assign new_sboxw[15 : 08] = sbox[sboxw[15 : 08]]; + assign new_sboxw[07 : 00] = sbox[sboxw[07 : 00]]; + + + //---------------------------------------------------------------- + // Creating the sbox array contents. //---------------------------------------------------------------- assign sbox[8'h00] = 8'h63; assign sbox[8'h01] = 8'h7c; @@ -309,12 +318,6 @@ module aes_sbox( assign sbox[8'hfe] = 8'hbb; assign sbox[8'hff] = 8'h16; - - assign new_sboxw[31 : 24] = sbox[sboxw[31 : 24]]; - assign new_sboxw[23 : 16] = sbox[sboxw[23 : 16]]; - assign new_sboxw[15 : 08] = sbox[sboxw[15 : 08]]; - assign new_sboxw[07 : 00] = sbox[sboxw[07 : 00]]; - endmodule // aes_sbox //====================================================================== -- cgit v1.2.3