core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Age	Commit message (Collapse)	Author
2018-05-22	Polished the wait_ready task to use defined bit index.	Joachim Strömbergson

2018-05-21	Increased number of inverse S-boxes to 16 and removed S-box scheduling.	Joachim Strömbergson

2018-05-21	Moved the Sbox used for key expansion into the key_mem.	Joachim Strömbergson

2018-05-21	Removed the sbox word mux. Removed ports for sbox access in the encipher ↵	Joachim Strömbergson
	datapath since it now has its own sboxes.
2018-05-21	Removed the sword counter since it is not needed.	Joachim Strömbergson

2018-05-21	Adding task to wait for ready to be set. This allows us to measure the ↵	Joachim Strömbergson
	number of cycles spent doing operations.
2017-12-15	Adding the error port that went missing. Sloppy.	Joachim Strömbergson

2017-12-14	Synced the AES core rtl and testbench to github. The updates does not add or ↵	Joachim Strömbergson
	modify any functionality, but silence a lot of warnings, reduce code size.
2015-12-13	whack copyrights	Paul Selkirk

2015-05-28	Corrected where config bits are.	Joachim Strömbergson

2015-05-16	(1) Changed name and version to reflect that it is not only AES-128 and that ↵	Joachim Strömbergson
	the core is fairly close to done. (2) Moved counter update.
2015-05-04	(1) Changed ordet of status and config addresses to conform to what we have ↵	Joachim Strömbergson
	in other cores. (2) Changed to localparam to stop polluting namespace.
2014-11-27	Adding testbenchs.	Joachim Strömbergson