core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Age	Commit message (Collapse)	Author
2018-10-03	Adding testcase that tests the mangling of aes operations by switching from ↵	Joachim Strömbergson
	encipher to decipher mid-operation.
2018-05-22	Combined all AES round operations into a single operation for a round.	Joachim Strömbergson

2018-05-22	Polished the wait_ready task to use defined bit index.	Joachim Strömbergson

2018-05-21	Increased number of inverse S-boxes to 16 and removed S-box scheduling.	Joachim Strömbergson

2018-05-21	Moved the Sbox used for key expansion into the key_mem.	Joachim Strömbergson

2018-05-21	Removed the sbox word mux. Removed ports for sbox access in the encipher ↵	Joachim Strömbergson
	datapath since it now has its own sboxes.
2018-05-21	Removed the sword counter since it is not needed.	Joachim Strömbergson

2018-05-21	Adding task to wait for ready to be set. This allows us to measure the ↵	Joachim Strömbergson
	number of cycles spent doing operations.
2018-05-21	Adding inital version of AES core optimized for performance.	Joachim Strömbergson