core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Age	Commit message (Expand)	Author
2018-10-03	Adding testcase that tests the mangling of aes operations by switching from e...	Joachim Strömbergson
2018-05-22	Combined all AES round operations into a single operation for a round.	Joachim Strömbergson
2018-05-22	Polished the wait_ready task to use defined bit index.	Joachim Strömbergson
2018-05-21	Increased number of inverse S-boxes to 16 and removed S-box scheduling.	Joachim Strömbergson
2018-05-21	Moved the Sbox used for key expansion into the key_mem.	Joachim Strömbergson
2018-05-21	Removed the sbox word mux. Removed ports for sbox access in the encipher data...	Joachim Strömbergson
2018-05-21	Removed the sword counter since it is not needed.	Joachim Strömbergson
2018-05-21	Adding task to wait for ready to be set. This allows us to measure the number...	Joachim Strömbergson
2017-12-15	Adding the error port that went missing. Sloppy.	Joachim Strömbergson
2017-12-14	Synced the AES core rtl and testbench to github. The updates does not add or ...	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-05-28	Corrected where config bits are.	Joachim Strömbergson
2015-05-16	(1) Changed name and version to reflect that it is not only AES-128 and that ...	Joachim Strömbergson
2015-05-04	(1) Changed ordet of status and config addresses to conform to what we have i...	Joachim Strömbergson
2014-11-27	Adding testbenchs.	Joachim Strömbergson