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-rw-r--r--src/rtl/aes.v23
-rw-r--r--src/rtl/aes_core.v45
-rw-r--r--src/rtl/aes_decipher_block.v196
-rw-r--r--src/rtl/aes_encipher_block.v209
-rw-r--r--src/rtl/aes_key_mem.v22
5 files changed, 119 insertions, 376 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index 4f668bc..492ba56 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -107,10 +107,6 @@ module aes(
reg [31 : 0] key_reg [0 : 7];
reg key_we;
- reg [127 : 0] result_reg;
- reg valid_reg;
- reg ready_reg;
-
//----------------------------------------------------------------
// Wires.
@@ -189,16 +185,9 @@ module aes(
next_reg <= 1'b0;
encdec_reg <= 1'b0;
keylen_reg <= 1'b0;
-
- result_reg <= 128'h0;
- valid_reg <= 1'b0;
- ready_reg <= 1'b0;
end
else
begin
- ready_reg <= core_ready;
- valid_reg <= core_valid;
- result_reg <= core_result;
init_reg <= init_new;
next_reg <= next_new;
@@ -239,10 +228,10 @@ module aes(
if (core_ready)
begin
if (address == ADDR_CTRL)
- begin
- init_new = write_data[CTRL_INIT_BIT];
- next_new = write_data[CTRL_NEXT_BIT];
- end
+ begin
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ end
if (address == ADDR_CONFIG)
config_we = 1'b1;
@@ -262,7 +251,7 @@ module aes(
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
- ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
+ ADDR_STATUS: tmp_read_data = {30'h0, core_valid, core_ready};
default:
begin
@@ -271,7 +260,7 @@ module aes(
if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
if (core_ready)
- tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
+ tmp_read_data = core_result[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
end
end
end // addr_decoder
diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v
index 5196a1f..518b20f 100644
--- a/src/rtl/aes_core.v
+++ b/src/rtl/aes_core.v
@@ -85,8 +85,6 @@ module aes_core(
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg init_state;
-
wire [127 : 0] round_key;
wire key_ready;
@@ -94,7 +92,6 @@ module aes_core(
wire [3 : 0] enc_round_nr;
wire [127 : 0] enc_new_block;
wire enc_ready;
- wire [31 : 0] enc_sboxw;
reg dec_next;
wire [3 : 0] dec_round_nr;
@@ -105,11 +102,6 @@ module aes_core(
reg [3 : 0] muxed_round_nr;
reg muxed_ready;
- wire [31 : 0] keymem_sboxw;
-
- reg [31 : 0] muxed_sboxw;
- wire [31 : 0] new_sboxw;
-
//----------------------------------------------------------------
// Instantiations.
@@ -124,9 +116,6 @@ module aes_core(
.round(enc_round_nr),
.round_key(round_key),
- .sboxw(enc_sboxw),
- .new_sboxw(new_sboxw),
-
.block(block),
.new_block(enc_new_block),
.ready(enc_ready)
@@ -159,15 +148,10 @@ module aes_core(
.round(muxed_round_nr),
.round_key(round_key),
- .ready(key_ready),
-
- .sboxw(keymem_sboxw),
- .new_sboxw(new_sboxw)
+ .ready(key_ready)
);
- aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
-
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
@@ -207,25 +191,6 @@ module aes_core(
//----------------------------------------------------------------
- // sbox_mux
- //
- // Controls which of the encipher datapath or the key memory
- // that gets access to the sbox.
- //----------------------------------------------------------------
- always @*
- begin : sbox_mux
- if (init_state)
- begin
- muxed_sboxw = keymem_sboxw;
- end
- else
- begin
- muxed_sboxw = enc_sboxw;
- end
- end // sbox_mux
-
-
- //----------------------------------------------------------------
// encdex_mux
//
// Controls which of the datapaths that get the next signal, have
@@ -264,7 +229,6 @@ module aes_core(
//----------------------------------------------------------------
always @*
begin : aes_core_ctrl
- init_state = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
result_valid_new = 1'b0;
@@ -277,7 +241,6 @@ module aes_core(
begin
if (init)
begin
- init_state = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
result_valid_new = 1'b0;
@@ -287,7 +250,6 @@ module aes_core(
end
else if (next)
begin
- init_state = 1'b0;
ready_new = 1'b0;
ready_we = 1'b1;
result_valid_new = 1'b0;
@@ -299,8 +261,6 @@ module aes_core(
CTRL_INIT:
begin
- init_state = 1'b1;
-
if (key_ready)
begin
ready_new = 1'b1;
@@ -312,8 +272,6 @@ module aes_core(
CTRL_NEXT:
begin
- init_state = 1'b0;
-
if (muxed_ready)
begin
ready_new = 1'b1;
@@ -327,7 +285,6 @@ module aes_core(
default:
begin
-
end
endcase // case (aes_core_ctrl_reg)
diff --git a/src/rtl/aes_decipher_block.v b/src/rtl/aes_decipher_block.v
index 82bdffb..b62065c 100644
--- a/src/rtl/aes_decipher_block.v
+++ b/src/rtl/aes_decipher_block.v
@@ -64,17 +64,14 @@ module aes_decipher_block(
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
- localparam NO_UPDATE = 3'h0;
- localparam INIT_UPDATE = 3'h1;
- localparam SBOX_UPDATE = 3'h2;
- localparam MAIN_UPDATE = 3'h3;
- localparam FINAL_UPDATE = 3'h4;
+ localparam NO_UPDATE = 2'h0;
+ localparam INIT_UPDATE = 2'h1;
+ localparam MAIN_UPDATE = 2'h2;
+ localparam FINAL_UPDATE = 2'h3;
- localparam CTRL_IDLE = 3'h0;
- localparam CTRL_INIT = 3'h1;
- localparam CTRL_SBOX = 3'h2;
- localparam CTRL_MAIN = 3'h3;
- localparam CTRL_FINAL = 3'h4;
+ localparam CTRL_IDLE = 2'h0;
+ localparam CTRL_INIT = 2'h1;
+ localparam CTRL_MAIN = 2'h2;
//----------------------------------------------------------------
@@ -192,11 +189,9 @@ module aes_decipher_block(
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
- reg [1 : 0] sword_ctr_reg;
- reg [1 : 0] sword_ctr_new;
- reg sword_ctr_we;
- reg sword_ctr_inc;
- reg sword_ctr_rst;
+ reg [127 : 0] block_reg;
+ reg [127 : 0] block_new;
+ reg block_we;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
@@ -204,44 +199,43 @@ module aes_decipher_block(
reg round_ctr_set;
reg round_ctr_dec;
- reg [127 : 0] block_new;
- reg [31 : 0] block_w0_reg;
- reg [31 : 0] block_w1_reg;
- reg [31 : 0] block_w2_reg;
- reg [31 : 0] block_w3_reg;
- reg block_w0_we;
- reg block_w1_we;
- reg block_w2_we;
- reg block_w3_we;
-
reg ready_reg;
reg ready_new;
reg ready_we;
- reg [2 : 0] dec_ctrl_reg;
- reg [2 : 0] dec_ctrl_new;
+ reg [1 : 0] dec_ctrl_reg;
+ reg [1 : 0] dec_ctrl_new;
reg dec_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [31 : 0] tmp_sboxw;
- wire [31 : 0] new_sboxw;
- reg [2 : 0] update_type;
+ reg [31 : 0] sboxw0;
+ reg [31 : 0] sboxw1;
+ reg [31 : 0] sboxw2;
+ reg [31 : 0] sboxw3;
+ wire [31 : 0] new_sboxw0;
+ wire [31 : 0] new_sboxw1;
+ wire [31 : 0] new_sboxw2;
+ wire [31 : 0] new_sboxw3;
+ reg [1 : 0] update_type;
//----------------------------------------------------------------
- // Instantiations.
+ // Inverse S-boxes.
//----------------------------------------------------------------
- aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw));
+ aes_inv_sbox inv_sbox_inst0(.sword(sboxw0), .new_sword(new_sboxw0));
+ aes_inv_sbox inv_sbox_inst1(.sword(sboxw1), .new_sword(new_sboxw1));
+ aes_inv_sbox inv_sbox_inst2(.sword(sboxw2), .new_sword(new_sboxw2));
+ aes_inv_sbox inv_sbox_inst3(.sword(sboxw3), .new_sword(new_sboxw3));
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
+ assign new_block = block_reg;
assign round = round_ctr_reg;
- assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
@@ -256,31 +250,15 @@ module aes_decipher_block(
begin: reg_update
if (!reset_n)
begin
- block_w0_reg <= 32'h0;
- block_w1_reg <= 32'h0;
- block_w2_reg <= 32'h0;
- block_w3_reg <= 32'h0;
- sword_ctr_reg <= 2'h0;
+ block_reg <= 128'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
dec_ctrl_reg <= CTRL_IDLE;
end
else
begin
- if (block_w0_we)
- block_w0_reg <= block_new[127 : 096];
-
- if (block_w1_we)
- block_w1_reg <= block_new[095 : 064];
-
- if (block_w2_we)
- block_w2_reg <= block_new[063 : 032];
-
- if (block_w3_we)
- block_w3_reg <= block_new[031 : 000];
-
- if (sword_ctr_we)
- sword_ctr_reg <= sword_ctr_new;
+ if (block_we)
+ block_reg <= block_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
@@ -301,86 +279,43 @@ module aes_decipher_block(
//----------------------------------------------------------------
always @*
begin : round_logic
- reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
+ reg [127 : 0] subbytes_block, inv_shiftrows_block, inv_mixcolumns_block;
reg [127 : 0] addkey_block;
inv_shiftrows_block = 128'h0;
inv_mixcolumns_block = 128'h0;
addkey_block = 128'h0;
block_new = 128'h0;
- tmp_sboxw = 32'h0;
- block_w0_we = 1'b0;
- block_w1_we = 1'b0;
- block_w2_we = 1'b0;
- block_w3_we = 1'b0;
+ block_we = 1'b0;
- old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ sboxw0 = block_reg[127 : 96];
+ sboxw1 = block_reg[95 : 64];
+ sboxw2 = block_reg[63 : 32];
+ sboxw3 = block_reg[31 : 0];
+ subbytes_block = {new_sboxw0, new_sboxw1, new_sboxw2, new_sboxw3};
- // Update based on update type.
case (update_type)
- // InitRound
INIT_UPDATE:
begin
- old_block = block;
- addkey_block = addroundkey(old_block, round_key);
+ addkey_block = addroundkey(block, round_key);
inv_shiftrows_block = inv_shiftrows(addkey_block);
block_new = inv_shiftrows_block;
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
- end
-
- SBOX_UPDATE:
- begin
- block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
-
- case (sword_ctr_reg)
- 2'h0:
- begin
- tmp_sboxw = block_w0_reg;
- block_w0_we = 1'b1;
- end
-
- 2'h1:
- begin
- tmp_sboxw = block_w1_reg;
- block_w1_we = 1'b1;
- end
-
- 2'h2:
- begin
- tmp_sboxw = block_w2_reg;
- block_w2_we = 1'b1;
- end
-
- 2'h3:
- begin
- tmp_sboxw = block_w3_reg;
- block_w3_we = 1'b1;
- end
- endcase // case (sbox_mux_ctrl_reg)
+ block_we = 1'b1;
end
MAIN_UPDATE:
begin
- addkey_block = addroundkey(old_block, round_key);
+ addkey_block = addroundkey(subbytes_block, round_key);
inv_mixcolumns_block = inv_mixcolumns(addkey_block);
inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
block_new = inv_shiftrows_block;
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
+ block_we = 1'b1;
end
FINAL_UPDATE:
begin
- block_new = addroundkey(old_block, round_key);
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
+ block_new = addroundkey(subbytes_block, round_key);
+ block_we = 1'b1;
end
default:
@@ -391,29 +326,6 @@ module aes_decipher_block(
//----------------------------------------------------------------
- // sword_ctr
- //
- // The subbytes word counter with reset and increase logic.
- //----------------------------------------------------------------
- always @*
- begin : sword_ctr
- sword_ctr_new = 2'h0;
- sword_ctr_we = 1'b0;
-
- if (sword_ctr_rst)
- begin
- sword_ctr_new = 2'h0;
- sword_ctr_we = 1'b1;
- end
- else if (sword_ctr_inc)
- begin
- sword_ctr_new = sword_ctr_reg + 1'b1;
- sword_ctr_we = 1'b1;
- end
- end // sword_ctr
-
-
- //----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
@@ -450,8 +362,6 @@ module aes_decipher_block(
//----------------------------------------------------------------
always @*
begin: decipher_ctrl
- sword_ctr_inc = 1'b0;
- sword_ctr_rst = 1'b0;
round_ctr_dec = 1'b0;
round_ctr_set = 1'b0;
ready_new = 1'b0;
@@ -475,32 +385,18 @@ module aes_decipher_block(
CTRL_INIT:
begin
- sword_ctr_rst = 1'b1;
+ round_ctr_dec = 1'b1;
update_type = INIT_UPDATE;
- dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_new = CTRL_MAIN;
dec_ctrl_we = 1'b1;
end
- CTRL_SBOX:
- begin
- sword_ctr_inc = 1'b1;
- update_type = SBOX_UPDATE;
- if (sword_ctr_reg == 2'h3)
- begin
- round_ctr_dec = 1'b1;
- dec_ctrl_new = CTRL_MAIN;
- dec_ctrl_we = 1'b1;
- end
- end
-
CTRL_MAIN:
begin
- sword_ctr_rst = 1'b1;
if (round_ctr_reg > 0)
begin
+ round_ctr_dec = 1'b1;
update_type = MAIN_UPDATE;
- dec_ctrl_new = CTRL_SBOX;
- dec_ctrl_we = 1'b1;
end
else
begin
diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v
index 094653a..f98d755 100644
--- a/src/rtl/aes_encipher_block.v
+++ b/src/rtl/aes_encipher_block.v
@@ -49,9 +49,6 @@ module aes_encipher_block(
output wire [3 : 0] round,
input wire [127 : 0] round_key,
- output wire [31 : 0] sboxw,
- input wire [31 : 0] new_sboxw,
-
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
@@ -67,17 +64,14 @@ module aes_encipher_block(
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
- localparam NO_UPDATE = 3'h0;
- localparam INIT_UPDATE = 3'h1;
- localparam SBOX_UPDATE = 3'h2;
- localparam MAIN_UPDATE = 3'h3;
- localparam FINAL_UPDATE = 3'h4;
+ localparam NO_UPDATE = 2'h0;
+ localparam INIT_UPDATE = 2'h1;
+ localparam MAIN_UPDATE = 2'h2;
+ localparam FINAL_UPDATE = 2'h3;
- localparam CTRL_IDLE = 3'h0;
- localparam CTRL_INIT = 3'h1;
- localparam CTRL_SBOX = 3'h2;
- localparam CTRL_MAIN = 3'h3;
- localparam CTRL_FINAL = 3'h4;
+ localparam CTRL_IDLE = 2'h0;
+ localparam CTRL_INIT = 2'h1;
+ localparam CTRL_MAIN = 2'h2;
//----------------------------------------------------------------
@@ -159,11 +153,9 @@ module aes_encipher_block(
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
- reg [1 : 0] sword_ctr_reg;
- reg [1 : 0] sword_ctr_new;
- reg sword_ctr_we;
- reg sword_ctr_inc;
- reg sword_ctr_rst;
+ reg [127 : 0] block_reg;
+ reg [127 : 0] block_new;
+ reg block_we;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
@@ -171,42 +163,48 @@ module aes_encipher_block(
reg round_ctr_rst;
reg round_ctr_inc;
- reg [127 : 0] block_new;
- reg [31 : 0] block_w0_reg;
- reg [31 : 0] block_w1_reg;
- reg [31 : 0] block_w2_reg;
- reg [31 : 0] block_w3_reg;
- reg block_w0_we;
- reg block_w1_we;
- reg block_w2_we;
- reg block_w3_we;
-
reg ready_reg;
reg ready_new;
reg ready_we;
- reg [2 : 0] enc_ctrl_reg;
- reg [2 : 0] enc_ctrl_new;
+ reg [1 : 0] enc_ctrl_reg;
+ reg [1 : 0] enc_ctrl_new;
reg enc_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [2 : 0] update_type;
- reg [31 : 0] muxed_sboxw;
+ reg [1 : 0] update_type;
+
+ reg [31 : 0] sboxw0;
+ reg [31 : 0] sboxw1;
+ reg [31 : 0] sboxw2;
+ reg [31 : 0] sboxw3;
+ wire [31 : 0] new_sboxw0;
+ wire [31 : 0] new_sboxw1;
+ wire [31 : 0] new_sboxw2;
+ wire [31 : 0] new_sboxw3;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
+ assign new_block = block_reg;
assign round = round_ctr_reg;
- assign sboxw = muxed_sboxw;
- assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
+ // Sboxes
+ //----------------------------------------------------------------
+ aes_sbox sbox_inst0(.sboxw(sboxw0), .new_sboxw(new_sboxw0));
+ aes_sbox sbox_inst1(.sboxw(sboxw1), .new_sboxw(new_sboxw1));
+ aes_sbox sbox_inst2(.sboxw(sboxw2), .new_sboxw(new_sboxw2));
+ aes_sbox sbox_inst3(.sboxw(sboxw3), .new_sboxw(new_sboxw3));
+
+
+ //----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
@@ -217,31 +215,15 @@ module aes_encipher_block(
begin: reg_update
if (!reset_n)
begin
- block_w0_reg <= 32'h0;
- block_w1_reg <= 32'h0;
- block_w2_reg <= 32'h0;
- block_w3_reg <= 32'h0;
- sword_ctr_reg <= 2'h0;
+ block_reg <= 128'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
enc_ctrl_reg <= CTRL_IDLE;
end
else
begin
- if (block_w0_we)
- block_w0_reg <= block_new[127 : 096];
-
- if (block_w1_we)
- block_w1_reg <= block_new[095 : 064];
-
- if (block_w2_we)
- block_w2_reg <= block_new[063 : 032];
-
- if (block_w3_we)
- block_w3_reg <= block_new[031 : 000];
-
- if (sword_ctr_we)
- sword_ctr_reg <= sword_ctr_new;
+ if (block_we)
+ block_reg <= block_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
@@ -262,18 +244,19 @@ module aes_encipher_block(
//----------------------------------------------------------------
always @*
begin : round_logic
- reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
+ reg [127 : 0] subbytes_block, shiftrows_block, mixcolumns_block;
reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
- block_new = 128'h0;
- muxed_sboxw = 32'h0;
- block_w0_we = 1'b0;
- block_w1_we = 1'b0;
- block_w2_we = 1'b0;
- block_w3_we = 1'b0;
+ block_new = 128'h0;
+ block_we = 1'b0;
- old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
- shiftrows_block = shiftrows(old_block);
+ sboxw0 = block_reg[127 : 96];
+ sboxw1 = block_reg[95 : 64];
+ sboxw2 = block_reg[63 : 32];
+ sboxw3 = block_reg[31 : 0];
+
+ subbytes_block = {new_sboxw0, new_sboxw1, new_sboxw2, new_sboxw3};
+ shiftrows_block = shiftrows(subbytes_block);
mixcolumns_block = mixcolumns(shiftrows_block);
addkey_init_block = addroundkey(block, round_key);
addkey_main_block = addroundkey(mixcolumns_block, round_key);
@@ -282,60 +265,20 @@ module aes_encipher_block(
case (update_type)
INIT_UPDATE:
begin
- block_new = addkey_init_block;
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
- end
-
- SBOX_UPDATE:
- begin
- block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
-
- case (sword_ctr_reg)
- 2'h0:
- begin
- muxed_sboxw = block_w0_reg;
- block_w0_we = 1'b1;
- end
-
- 2'h1:
- begin
- muxed_sboxw = block_w1_reg;
- block_w1_we = 1'b1;
- end
-
- 2'h2:
- begin
- muxed_sboxw = block_w2_reg;
- block_w2_we = 1'b1;
- end
-
- 2'h3:
- begin
- muxed_sboxw = block_w3_reg;
- block_w3_we = 1'b1;
- end
- endcase // case (sbox_mux_ctrl_reg)
+ block_new = addkey_init_block;
+ block_we = 1'b1;
end
MAIN_UPDATE:
begin
- block_new = addkey_main_block;
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
+ block_new = addkey_main_block;
+ block_we = 1'b1;
end
FINAL_UPDATE:
begin
- block_new = addkey_final_block;
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
+ block_new = addkey_final_block;
+ block_we = 1'b1;
end
default:
@@ -346,29 +289,6 @@ module aes_encipher_block(
//----------------------------------------------------------------
- // sword_ctr
- //
- // The subbytes word counter with reset and increase logic.
- //----------------------------------------------------------------
- always @*
- begin : sword_ctr
- sword_ctr_new = 2'h0;
- sword_ctr_we = 1'b0;
-
- if (sword_ctr_rst)
- begin
- sword_ctr_new = 2'h0;
- sword_ctr_we = 1'b1;
- end
- else if (sword_ctr_inc)
- begin
- sword_ctr_new = sword_ctr_reg + 1'b1;
- sword_ctr_we = 1'b1;
- end
- end // sword_ctr
-
-
- //----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
@@ -401,16 +321,10 @@ module aes_encipher_block(
reg [3 : 0] num_rounds;
if (keylen == AES_256_BIT_KEY)
- begin
- num_rounds = AES256_ROUNDS;
- end
+ num_rounds = AES256_ROUNDS;
else
- begin
- num_rounds = AES128_ROUNDS;
- end
+ num_rounds = AES128_ROUNDS;
- sword_ctr_inc = 1'b0;
- sword_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
round_ctr_rst = 1'b0;
ready_new = 1'b0;
@@ -435,32 +349,17 @@ module aes_encipher_block(
CTRL_INIT:
begin
round_ctr_inc = 1'b1;
- sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
- enc_ctrl_new = CTRL_SBOX;
+ enc_ctrl_new = CTRL_MAIN;
enc_ctrl_we = 1'b1;
end
- CTRL_SBOX:
- begin
- sword_ctr_inc = 1'b1;
- update_type = SBOX_UPDATE;
- if (sword_ctr_reg == 2'h3)
- begin
- enc_ctrl_new = CTRL_MAIN;
- enc_ctrl_we = 1'b1;
- end
- end
-
CTRL_MAIN:
begin
- sword_ctr_rst = 1'b1;
round_ctr_inc = 1'b1;
if (round_ctr_reg < num_rounds)
begin
update_type = MAIN_UPDATE;
- enc_ctrl_new = CTRL_SBOX;
- enc_ctrl_we = 1'b1;
end
else
begin
diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
index f57d4dd..07e338f 100644
--- a/src/rtl/aes_key_mem.v
+++ b/src/rtl/aes_key_mem.v
@@ -47,11 +47,7 @@ module aes_key_mem(
input wire [3 : 0] round,
output wire [127 : 0] round_key,
- output wire ready,
-
-
- output wire [31 : 0] sboxw,
- input wire [31 : 0] new_sboxw
+ output wire ready
);
@@ -109,7 +105,8 @@ module aes_key_mem(
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [31 : 0] tmp_sboxw;
+ reg [31 : 0] sboxw;
+ wire [31 : 0] new_sboxw;
reg round_key_update;
reg [3 : 0] num_rounds;
@@ -122,7 +119,12 @@ module aes_key_mem(
//----------------------------------------------------------------
assign round_key = tmp_round_key;
assign ready = ready_reg;
- assign sboxw = tmp_sboxw;
+
+
+ //----------------------------------------------------------------
+ // S-box for key expansion.
+ //----------------------------------------------------------------
+ aes_sbox sbox_inst(.sboxw(sboxw), .new_sboxw(new_sboxw));
//----------------------------------------------------------------
@@ -141,11 +143,11 @@ module aes_key_mem(
for (i = 0 ; i < 15 ; i = i + 1)
key_mem [i] <= 128'h0;
- prev_key0_reg <= 128'h0;
- prev_key1_reg <= 128'h0;
rcon_reg <= 8'h0;
ready_reg <= 1'b0;
round_ctr_reg <= 4'h0;
+ prev_key0_reg <= 128'h0;
+ prev_key1_reg <= 128'h0;
key_mem_ctrl_reg <= CTRL_IDLE;
end
else
@@ -225,7 +227,7 @@ module aes_key_mem(
w7 = prev_key1_reg[031 : 000];
rconw = {rcon_reg, 24'h0};
- tmp_sboxw = w7;
+ sboxw = w7;
rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
trw = rotstw ^ rconw;
tw = new_sboxw;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 07:46:51 +0000