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-rw-r--r--src/rtl/aes.v6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index c2b333a..0d719d2 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -49,7 +49,8 @@ module aes(
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
- output wire [31 : 0] read_data
+ output wire [31 : 0] read_data,
+ output wire error
);
//----------------------------------------------------------------
@@ -115,6 +116,7 @@ module aes(
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
+ reg tmp_error;
wire core_encdec;
wire core_init;
@@ -131,6 +133,7 @@ module aes(
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
+ assign error = tmp_error;
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
@@ -227,6 +230,7 @@ module aes(
key_we = 1'b0;
block_we = 1'b0;
tmp_read_data = 32'h0;
+ tmp_error = 1'b0;
if (cs)
begin