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Diffstat (limited to 'src/rtl/aes_key_mem.v')
-rw-r--r--src/rtl/aes_key_mem.v22
1 files changed, 12 insertions, 10 deletions
diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
index f57d4dd..07e338f 100644
--- a/src/rtl/aes_key_mem.v
+++ b/src/rtl/aes_key_mem.v
@@ -47,11 +47,7 @@ module aes_key_mem(
input wire [3 : 0] round,
output wire [127 : 0] round_key,
- output wire ready,
-
-
- output wire [31 : 0] sboxw,
- input wire [31 : 0] new_sboxw
+ output wire ready
);
@@ -109,7 +105,8 @@ module aes_key_mem(
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [31 : 0] tmp_sboxw;
+ reg [31 : 0] sboxw;
+ wire [31 : 0] new_sboxw;
reg round_key_update;
reg [3 : 0] num_rounds;
@@ -122,7 +119,12 @@ module aes_key_mem(
//----------------------------------------------------------------
assign round_key = tmp_round_key;
assign ready = ready_reg;
- assign sboxw = tmp_sboxw;
+
+
+ //----------------------------------------------------------------
+ // S-box for key expansion.
+ //----------------------------------------------------------------
+ aes_sbox sbox_inst(.sboxw(sboxw), .new_sboxw(new_sboxw));
//----------------------------------------------------------------
@@ -141,11 +143,11 @@ module aes_key_mem(
for (i = 0 ; i < 15 ; i = i + 1)
key_mem [i] <= 128'h0;
- prev_key0_reg <= 128'h0;
- prev_key1_reg <= 128'h0;
rcon_reg <= 8'h0;
ready_reg <= 1'b0;
round_ctr_reg <= 4'h0;
+ prev_key0_reg <= 128'h0;
+ prev_key1_reg <= 128'h0;
key_mem_ctrl_reg <= CTRL_IDLE;
end
else
@@ -225,7 +227,7 @@ module aes_key_mem(
w7 = prev_key1_reg[031 : 000];
rconw = {rcon_reg, 24'h0};
- tmp_sboxw = w7;
+ sboxw = w7;
rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
trw = rotstw ^ rconw;
tw = new_sboxw;