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Diffstat (limited to 'src/rtl/aes_decipher_block.v')
-rw-r--r--src/rtl/aes_decipher_block.v196
1 files changed, 46 insertions, 150 deletions
diff --git a/src/rtl/aes_decipher_block.v b/src/rtl/aes_decipher_block.v
index 82bdffb..b62065c 100644
--- a/src/rtl/aes_decipher_block.v
+++ b/src/rtl/aes_decipher_block.v
@@ -64,17 +64,14 @@ module aes_decipher_block(
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
- localparam NO_UPDATE = 3'h0;
- localparam INIT_UPDATE = 3'h1;
- localparam SBOX_UPDATE = 3'h2;
- localparam MAIN_UPDATE = 3'h3;
- localparam FINAL_UPDATE = 3'h4;
+ localparam NO_UPDATE = 2'h0;
+ localparam INIT_UPDATE = 2'h1;
+ localparam MAIN_UPDATE = 2'h2;
+ localparam FINAL_UPDATE = 2'h3;
- localparam CTRL_IDLE = 3'h0;
- localparam CTRL_INIT = 3'h1;
- localparam CTRL_SBOX = 3'h2;
- localparam CTRL_MAIN = 3'h3;
- localparam CTRL_FINAL = 3'h4;
+ localparam CTRL_IDLE = 2'h0;
+ localparam CTRL_INIT = 2'h1;
+ localparam CTRL_MAIN = 2'h2;
//----------------------------------------------------------------
@@ -192,11 +189,9 @@ module aes_decipher_block(
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
- reg [1 : 0] sword_ctr_reg;
- reg [1 : 0] sword_ctr_new;
- reg sword_ctr_we;
- reg sword_ctr_inc;
- reg sword_ctr_rst;
+ reg [127 : 0] block_reg;
+ reg [127 : 0] block_new;
+ reg block_we;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
@@ -204,44 +199,43 @@ module aes_decipher_block(
reg round_ctr_set;
reg round_ctr_dec;
- reg [127 : 0] block_new;
- reg [31 : 0] block_w0_reg;
- reg [31 : 0] block_w1_reg;
- reg [31 : 0] block_w2_reg;
- reg [31 : 0] block_w3_reg;
- reg block_w0_we;
- reg block_w1_we;
- reg block_w2_we;
- reg block_w3_we;
-
reg ready_reg;
reg ready_new;
reg ready_we;
- reg [2 : 0] dec_ctrl_reg;
- reg [2 : 0] dec_ctrl_new;
+ reg [1 : 0] dec_ctrl_reg;
+ reg [1 : 0] dec_ctrl_new;
reg dec_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [31 : 0] tmp_sboxw;
- wire [31 : 0] new_sboxw;
- reg [2 : 0] update_type;
+ reg [31 : 0] sboxw0;
+ reg [31 : 0] sboxw1;
+ reg [31 : 0] sboxw2;
+ reg [31 : 0] sboxw3;
+ wire [31 : 0] new_sboxw0;
+ wire [31 : 0] new_sboxw1;
+ wire [31 : 0] new_sboxw2;
+ wire [31 : 0] new_sboxw3;
+ reg [1 : 0] update_type;
//----------------------------------------------------------------
- // Instantiations.
+ // Inverse S-boxes.
//----------------------------------------------------------------
- aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw));
+ aes_inv_sbox inv_sbox_inst0(.sword(sboxw0), .new_sword(new_sboxw0));
+ aes_inv_sbox inv_sbox_inst1(.sword(sboxw1), .new_sword(new_sboxw1));
+ aes_inv_sbox inv_sbox_inst2(.sword(sboxw2), .new_sword(new_sboxw2));
+ aes_inv_sbox inv_sbox_inst3(.sword(sboxw3), .new_sword(new_sboxw3));
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
+ assign new_block = block_reg;
assign round = round_ctr_reg;
- assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
@@ -256,31 +250,15 @@ module aes_decipher_block(
begin: reg_update
if (!reset_n)
begin
- block_w0_reg <= 32'h0;
- block_w1_reg <= 32'h0;
- block_w2_reg <= 32'h0;
- block_w3_reg <= 32'h0;
- sword_ctr_reg <= 2'h0;
+ block_reg <= 128'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
dec_ctrl_reg <= CTRL_IDLE;
end
else
begin
- if (block_w0_we)
- block_w0_reg <= block_new[127 : 096];
-
- if (block_w1_we)
- block_w1_reg <= block_new[095 : 064];
-
- if (block_w2_we)
- block_w2_reg <= block_new[063 : 032];
-
- if (block_w3_we)
- block_w3_reg <= block_new[031 : 000];
-
- if (sword_ctr_we)
- sword_ctr_reg <= sword_ctr_new;
+ if (block_we)
+ block_reg <= block_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
@@ -301,86 +279,43 @@ module aes_decipher_block(
//----------------------------------------------------------------
always @*
begin : round_logic
- reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
+ reg [127 : 0] subbytes_block, inv_shiftrows_block, inv_mixcolumns_block;
reg [127 : 0] addkey_block;
inv_shiftrows_block = 128'h0;
inv_mixcolumns_block = 128'h0;
addkey_block = 128'h0;
block_new = 128'h0;
- tmp_sboxw = 32'h0;
- block_w0_we = 1'b0;
- block_w1_we = 1'b0;
- block_w2_we = 1'b0;
- block_w3_we = 1'b0;
+ block_we = 1'b0;
- old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ sboxw0 = block_reg[127 : 96];
+ sboxw1 = block_reg[95 : 64];
+ sboxw2 = block_reg[63 : 32];
+ sboxw3 = block_reg[31 : 0];
+ subbytes_block = {new_sboxw0, new_sboxw1, new_sboxw2, new_sboxw3};
- // Update based on update type.
case (update_type)
- // InitRound
INIT_UPDATE:
begin
- old_block = block;
- addkey_block = addroundkey(old_block, round_key);
+ addkey_block = addroundkey(block, round_key);
inv_shiftrows_block = inv_shiftrows(addkey_block);
block_new = inv_shiftrows_block;
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
- end
-
- SBOX_UPDATE:
- begin
- block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
-
- case (sword_ctr_reg)
- 2'h0:
- begin
- tmp_sboxw = block_w0_reg;
- block_w0_we = 1'b1;
- end
-
- 2'h1:
- begin
- tmp_sboxw = block_w1_reg;
- block_w1_we = 1'b1;
- end
-
- 2'h2:
- begin
- tmp_sboxw = block_w2_reg;
- block_w2_we = 1'b1;
- end
-
- 2'h3:
- begin
- tmp_sboxw = block_w3_reg;
- block_w3_we = 1'b1;
- end
- endcase // case (sbox_mux_ctrl_reg)
+ block_we = 1'b1;
end
MAIN_UPDATE:
begin
- addkey_block = addroundkey(old_block, round_key);
+ addkey_block = addroundkey(subbytes_block, round_key);
inv_mixcolumns_block = inv_mixcolumns(addkey_block);
inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
block_new = inv_shiftrows_block;
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
+ block_we = 1'b1;
end
FINAL_UPDATE:
begin
- block_new = addroundkey(old_block, round_key);
- block_w0_we = 1'b1;
- block_w1_we = 1'b1;
- block_w2_we = 1'b1;
- block_w3_we = 1'b1;
+ block_new = addroundkey(subbytes_block, round_key);
+ block_we = 1'b1;
end
default:
@@ -391,29 +326,6 @@ module aes_decipher_block(
//----------------------------------------------------------------
- // sword_ctr
- //
- // The subbytes word counter with reset and increase logic.
- //----------------------------------------------------------------
- always @*
- begin : sword_ctr
- sword_ctr_new = 2'h0;
- sword_ctr_we = 1'b0;
-
- if (sword_ctr_rst)
- begin
- sword_ctr_new = 2'h0;
- sword_ctr_we = 1'b1;
- end
- else if (sword_ctr_inc)
- begin
- sword_ctr_new = sword_ctr_reg + 1'b1;
- sword_ctr_we = 1'b1;
- end
- end // sword_ctr
-
-
- //----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
@@ -450,8 +362,6 @@ module aes_decipher_block(
//----------------------------------------------------------------
always @*
begin: decipher_ctrl
- sword_ctr_inc = 1'b0;
- sword_ctr_rst = 1'b0;
round_ctr_dec = 1'b0;
round_ctr_set = 1'b0;
ready_new = 1'b0;
@@ -475,32 +385,18 @@ module aes_decipher_block(
CTRL_INIT:
begin
- sword_ctr_rst = 1'b1;
+ round_ctr_dec = 1'b1;
update_type = INIT_UPDATE;
- dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_new = CTRL_MAIN;
dec_ctrl_we = 1'b1;
end
- CTRL_SBOX:
- begin
- sword_ctr_inc = 1'b1;
- update_type = SBOX_UPDATE;
- if (sword_ctr_reg == 2'h3)
- begin
- round_ctr_dec = 1'b1;
- dec_ctrl_new = CTRL_MAIN;
- dec_ctrl_we = 1'b1;
- end
- end
-
CTRL_MAIN:
begin
- sword_ctr_rst = 1'b1;
if (round_ctr_reg > 0)
begin
+ round_ctr_dec = 1'b1;
update_type = MAIN_UPDATE;
- dec_ctrl_new = CTRL_SBOX;
- dec_ctrl_we = 1'b1;
end
else
begin
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 02:33:15 +0000