diff options
Diffstat (limited to 'src/rtl/aes_core.v')
| -rw-r--r-- | src/rtl/aes_core.v | 45 |
1 files changed, 1 insertions, 44 deletions
diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v index 5196a1f..518b20f 100644 --- a/src/rtl/aes_core.v +++ b/src/rtl/aes_core.v @@ -85,8 +85,6 @@ module aes_core( //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- - reg init_state; - wire [127 : 0] round_key; wire key_ready; @@ -94,7 +92,6 @@ module aes_core( wire [3 : 0] enc_round_nr; wire [127 : 0] enc_new_block; wire enc_ready; - wire [31 : 0] enc_sboxw; reg dec_next; wire [3 : 0] dec_round_nr; @@ -105,11 +102,6 @@ module aes_core( reg [3 : 0] muxed_round_nr; reg muxed_ready; - wire [31 : 0] keymem_sboxw; - - reg [31 : 0] muxed_sboxw; - wire [31 : 0] new_sboxw; - //---------------------------------------------------------------- // Instantiations. @@ -124,9 +116,6 @@ module aes_core( .round(enc_round_nr), .round_key(round_key), - .sboxw(enc_sboxw), - .new_sboxw(new_sboxw), - .block(block), .new_block(enc_new_block), .ready(enc_ready) @@ -159,15 +148,10 @@ module aes_core( .round(muxed_round_nr), .round_key(round_key), - .ready(key_ready), - - .sboxw(keymem_sboxw), - .new_sboxw(new_sboxw) + .ready(key_ready) ); - aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw)); - //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -207,25 +191,6 @@ module aes_core( //---------------------------------------------------------------- - // sbox_mux - // - // Controls which of the encipher datapath or the key memory - // that gets access to the sbox. - //---------------------------------------------------------------- - always @* - begin : sbox_mux - if (init_state) - begin - muxed_sboxw = keymem_sboxw; - end - else - begin - muxed_sboxw = enc_sboxw; - end - end // sbox_mux - - - //---------------------------------------------------------------- // encdex_mux // // Controls which of the datapaths that get the next signal, have @@ -264,7 +229,6 @@ module aes_core( //---------------------------------------------------------------- always @* begin : aes_core_ctrl - init_state = 1'b0; ready_new = 1'b0; ready_we = 1'b0; result_valid_new = 1'b0; @@ -277,7 +241,6 @@ module aes_core( begin if (init) begin - init_state = 1'b1; ready_new = 1'b0; ready_we = 1'b1; result_valid_new = 1'b0; @@ -287,7 +250,6 @@ module aes_core( end else if (next) begin - init_state = 1'b0; ready_new = 1'b0; ready_we = 1'b1; result_valid_new = 1'b0; @@ -299,8 +261,6 @@ module aes_core( CTRL_INIT: begin - init_state = 1'b1; - if (key_ready) begin ready_new = 1'b1; @@ -312,8 +272,6 @@ module aes_core( CTRL_NEXT: begin - init_state = 1'b0; - if (muxed_ready) begin ready_new = 1'b1; @@ -327,7 +285,6 @@ module aes_core( default: begin - end endcase // case (aes_core_ctrl_reg) |